With semiconductor technology scaling to the 22nm node and beyond, FinFET has started replacing CMOS, for its superior control of short-channel effects. However, process, supply voltage, and temperature(PVT) variations across the integrated circuit(IC) become worse with technology scaling. Thus, to analyze timing and power under PVT variations, statistical analysis/optimization techniques are more suitable than static timing/power analysis and optimization counterparts. In this paper, we propose a statistical optimization framework using dual device-type assignment at the architecture level under PVT variations that takes spatial correlations into account, and leverages circuit-level statistical analysis techniques. To the best of our knowledge, this is the first work to study statistical optimization at the system level under PVT variations. Simulation results show that leakage power yield and dynamic power yield can be improved by up to 44.2% and 21.2%, for a single-core processor and up to 43.0% and 50.0%, for an 8-core chip multiprocessor (CMP). Under the same(99.0%) power yield constraints, leakage power and dynamic power are reduced by up to 91.2% and 4.3%, for a single-core processor, and up to 44.6% and 12.5%, for an 8-core CMP. We also show that optimizations performed without taking module-to-module and core-to-core spatial correlations into account overestimate yield, establishing the importance of taking such correlations into account.
Security is becoming a de-facto requirement of System-on-Chips (SoC), leading up to a significant share of circuit design cost. In this paper, we propose an advanced SBUS protocol (ASBUS), in order to improve the data feeding efficiency of the Advanced Encryption Standard (AES) encrypted circuits. As a case study, the direct memory access (DMA) combined with AES engine and memory controller are implemented as our design-under-test (DUT) using field-programmable gate arrays (FPGA). The results show that our presented ASBUS structure outperforms the AXI-based design for cipher tests. As an example, the 32-bit ASBUS design costs less in terms of hardware resources and achieves higher throughput ($1.30 \times$) than the 32-bit AXI implementation, and the dynamic energy consumed by the ASBUS cipher test is reduced to 71.27\% compared with the AXI test.
Microfluidic technology offers promise for implementing biochemistry-on-chip with diverse applications to clinical diagnosis, drug design, and point-of-care testing. Among various types of fluid-chips, droplet-based digital microfluidic biochips (DMFBs) provide the advantage of programmability. However, because of manufacturing defects, electrode degradation, or dielectric breakdown, these chips may suffer from incorrect fluidic behavior. Reliability is of utmost concern in DMFBs used for safety-critical bio-protocols. Various methods are deployed to test these devices, either as off-line, or being overlapped with bioassay operations (concurrent or in-field testing). The main challenge of in-field testing is the test must run concurrently with the execution of the normal assay without hampering the correctness of the latter. In prior work, Eulerian path based models have been studied for off-line testing; no such effort was made in the area of concurrent testing. We propose, for in-field application, a SAT-based technique to find an optimal test plan that can be used to check droplet movement across the boundary between every pair of adjacent electrodes, which is visited by the droplets of the ongoing assay. The proposed method determines a test solution without hampering the assay operations. Experiments on several test-cases demonstrate the effectiveness of the method w.r.t. test-completion time.
3D-DRAMs are emerging as a promising solution to address the memory wall problem in computer systems. However, high fabrication cost per bit and thermal issues are the main reasons that prevent architects from using 3D-DRAM alone as the main memory building block. In this paper, we address this issue by proposing a heterogeneous memory system that combines a DDRx DRAM with an emerging 3D hybrid memory cube (HMC) technology. Bandwidth and temperature management are the challenging issues for this heterogeneous memory architecture. To address these challenges, first we introduce a memory page allocation policy for the heterogeneous memory system to maximize performance. Then, using the proposed policy, we introduce a temperature-aware algorithm that dynamically distributes the requested bandwidth between HMC and DDRx DRAM to reduce the thermal hotspot while maintaining high performance. We take into account the impact of both core count and HMC channel count on performance while using the proposed policies. The results show that the proposed memory page allocation policy can utilize the memory bandwidth close to 99% of the ideal bandwidth utilization. Moreover, our temperate-aware bandwidth adaptation reduces the average steady-state temperature of the HMC hotspot across various workloads by 4.5K while incurring 2.5% performance overhead.