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Editorial: Special issue on 3D integrated circuits and microarchitectures
Yuan Xie, Jason Cong, Paul Franzon
Article No.: 15
PicoServer: Using 3D stacking technology to build energy efficient servers
Taeho Kgil, Ali Saidi, Nathan Binkert, Steve Reinhardt, Krisztian Flautner, Trevor Mudge
Article No.: 16
This article extends our prior work to show that a straightforward use of 3D stacking technology enables the design of compact energy-efficient servers. Our proposed architecture, called PicoServer, employs 3D technology to bond one die containing...
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design
Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong
Article No.: 17
In this article we propose techniques that enable efficient exploration of the 3D design space, where each logical block can span more than one silicon layer. Fine-grain 3D integration provides reduced intrablock wire delay as well as improved...
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
Yong Zhan, Sachin S. Sapatnekar
Article No.: 18
With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a critical issue in today's VLSI designs, especially for 3D IC technologies. To...
Parametric yield management for 3D ICs: Models and strategies for improvement
Cesare Ferri, Sherief Reda, R. Iris Bahar
Article No.: 19
Three-Dimensional (3D) Integrated Circuits (ICs) that integrate die with Through-Silicon Vias (TSVs) promise to continue system and functionality scaling beyond the traditional geometric 2D device scaling. 3D integration also improves the...
Multilayer stacking technology using wafer-to-wafer stacked method
Nobuaki Miyakawa, Eiri Hashimoto, Takanori Maebashi, Natsuo Nakamura, Yutaka Sacho, Shigeto Nakayama, Shinjiro Toyoda
Article No.: 20
We have developed a new three-dimensional stacking technology using the wafer-to-wafer stacked method. Electrical conductivity between each wafer is almost 100% and contact resistance is less than 0.7Ω between a through-silicon via...