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Emerging Technologies in Computing (JETC)

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ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 9 Issue 3, September 2013

Design of efficient reversible logic-based binary and BCD adder circuits
Himanshu Thapliyal, Nagarajan Ranganathan
Article No.: 17
DOI: 10.1145/2491682

Reversible logic is gaining significance in the context of emerging technologies such as quantum computing since reversible circuits do not lose information during computation and there is one-to-one mapping between the inputs and outputs. In this...

Color image processing with multi-peak resonant tunneling diodes
Woo Hyung Lee, Pinaki Mazumder
Article No.: 18
DOI: 10.1145/2503128

The article introduces a novel approach to color image processing that utilizes multi-peak resonant tunneling diodes for encoding color information in quantized states of the diodes. The Multi-Peak Resonant Tunneling Diodes (MPRTDs) are organized...

Cell transformations and physical design techniques for 3D monolithic integrated circuits
Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Giovanni de Micheli
Article No.: 19
DOI: 10.1145/2491675

3D Monolithic Integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100nm. Given the...

Design space exploration of FinFET cache
Aoxiang Tang, Niraj K. Jha
Article No.: 20
DOI: 10.1145/2491678

Integration of cache on-chip has significantly improved the performance of modern processors. The relentless demand for ever-increasing performance has led to the need to increase the cache capacity and number of cache levels. However, the...

ILP formulations for variation/defect-tolerant logic mapping on crossbar nano-architectures
Masoud Zamani, Hanieh Mirzaei, Mehdi B. Tahoori
Article No.: 21
DOI: 10.1145/2491680

Several emerging nano-technologies, including crossbar nano-architectures, have recently been studied as possible replacement or supplement to CMOS technology in the future. However, extreme process variation and high failure rates, mainly due to...

Exploring the vulnerability of CMPs to soft errors with 3D stacked nonvolatile memory
Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie
Article No.: 22
DOI: 10.1145/2491679

Improving the vulnerability to soft errors is one of the important design goals for future architecture design of Chip-MultiProcessors (CMPs). In this study, we explore the soft error characteristics of CMPs with 3D stacked NonVolatile Memory...

NBTI-aware circuit node criticality computation
Shengqi Yang, Wenping Wang, Mark Hagan, Wei Zhang, Pallav Gupta, Yu Cao
Article No.: 23
DOI: 10.1145/2491681

For sub-65nm technology nodes, Negative Bias Temperature Instability (NBTI) has become a primary limiting factor of circuit lifetime. During the past few years, researchers have spent considerable effort on accurate modeling and characterization...

Complex network-enabled robust wireless network-on-chip architectures
Paul Wettin, Anuroop Vidapalapati, Amlan Gangul, Partha Pratim Pande
Article No.: 24
DOI: 10.1145/2491676

The Network-on-Chip (NoC) paradigm has emerged as a scalable interconnection infrastructure for modern multicore chips. However, with growing levels of integration, the traditional NoCs suffer from high latency and energy dissipation in on-chip...

Detection of trojans using a combined ring oscillator network and off-chip transient power analysis
Xuehui Zhang, Andrew Ferraiuolo, Mohammad Tehranipoor
Article No.: 25
DOI: 10.1145/2491677

Verifying the trustworthiness of Integrated Circuits (ICs) is of utmost importance, as hardware Trojans may destroy ICs bound for critical applications. A novel methodology combining on-chip structure with external current measurements is proposed...