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Emerging Technologies in Computing (JETC)

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ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 10 Issue 2, February 2014

Critical-reliability path identification and delay analysis
Jifeng Chen, Shuo Wang, Mohammad Tehranipoor
Article No.: 12
DOI: 10.1145/2564926

Circuit reliability analysis at the presilicon stage has become vital for sub-45nm technology designs in particular, due to aging effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI). To avoid potential...

Delay-based processing-in-wire for design of QCA serial decimal arithmetic units
Michael Gladshtein
Article No.: 13
DOI: 10.1145/2564927

Quantum-dot cellular automata (QCA) technology is now considered to be one of the prospective technologies for a nanocomputer creation. The physical properties of QCA and its expanding range of computer applications make it expedient to use the...

RMDDS: Reed-muller decision diagram synthesis of reversible logic circuits
Chia-Chun Lin, Niraj K. Jha
Article No.: 14
DOI: 10.1145/2564923

In this article, we propose a flexible and efficient reversible logic synthesizer. It exploits the complementary advantages of two methods: Reed-Muller Reversible Logic Synthesis (RMRLS) and Decision Diagram Synthesis (DDS), and is thus called...

On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip
Weichen Liu, Xuan Wang, Jiang Xu, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang
Article No.: 15
DOI: 10.1145/2564928

As transistor density continues to increase with the advent of nanotechnology, reliability issues raised by the more frequent appearance of soft errors are becoming critical for future embedded multiprocessor systems design. State-of-the-art...

Inexact computing using probabilistic circuits: Ultra low-power digital processing
Jaeyoon Kim, Sandip Tiwari
Article No.: 16
DOI: 10.1145/2564925

Numerous computing applications can tolerate low error rates. In such applications, inexact approaches provide the ability to achieve significantly lower power. This work demonstrates the power-error trade-offs that can be achieved. Using...

Nanopipelined threshold network synthesis
Luke Pierce, Spyros Tragoudas
Article No.: 17
DOI: 10.1145/2564924

Threshold logic gates allow for complex multiinput functions to be implemented using a single gate thereby reducing the power and area of a circuit. Clocked threshold gates are nanopipelined to increase network throughput. It is shown that...

A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs
Dong Xiang, Kele Shen
Article No.: 18
DOI: 10.1145/2564922

The three-dimensional (3-D) technology offers a new solution to the increasing density of integrated circuits (ICs). In this work, we propose novel scan architectures for 3-D IC pre-bond and post-bond testing by considering the interconnection...