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mNoC: Large Nanophotonic Network-on-Chip Crossbars with Molecular Scale Devices
Jun Pang, Christopher Dwyer, Alvin R. Lebeck
Article No.: 1
Moore's law and the continuity of device scaling have led to an increasing number of cores/nodes on a chip, creating a need for new mechanisms to achieve high-performance and power-efficient Network-on-Chip (NoC). Nanophotonics based NoCs...
Multilayer Graphene Nanoribbon and Carbon Nanotube Based Floating Gate Transistor for Nonvolatile Flash Memory
Nahid M. Hossain, Masud H. Chowdhury
Article No.: 2
Floating gate transistor is the fundamental building block of nonvolatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. Recently there has been a surge of interest to introduce...
A Low-Power Variation-Aware Adaptive Write Scheme for Access-Transistor-Free Memristive Memory
Amirali Ghofrani, Miguel-angel lastras-montaño, Siddharth Gaba, Melika Payvand, Wei Lu, Luke Theogarajan, Kwang-Ting Cheng
Article No.: 3
Recent advances in access-transistor-free memristive crossbars have demonstrated the potential of memristor arrays as high-density and ultra-low-power memory. However, with considerable variations in the write-time characteristics of individual...
Energy-Efficient All-Spin Cache Hierarchy Using Shift-Based Writes and Multilevel Storage
Rangharajan Venkatesan, Mrigank Sharad, Kaushik Roy, Anand Raghunathan
Article No.: 4
Spintronic memories are considered to be promising candidates for future on-chip memories due to their high density, nonvolatility, and near-zero leakage. However, they also face challenges such as high write energy and latency and limited read...
MN-MATE: Elastic Resource Management of Manycores and a Hybrid Memory Hierarchy for a Cloud Node
Kyu Ho Park, Woomin Hwang, Hyunchul Seok, Chulmin Kim, Dong-jae Shin, Dong Jin Kim, Min Kyu Maeng, Seong Min Kim
Article No.: 5
Recent advent of manycore system increases needs for larger but faster memory hierarchy. Emerging next generation memories such as on-chip DRAM and nonvolatile memory (NVRAM) are promising candidates for replacement of DRAM-only main memory....
A Write-Aware STTRAM-Based Register File Architecture for GPGPU
Jue Wang, Yuan Xie
Article No.: 6
The massively parallel processing capacity of GPGPUs requires a large register file (RF), and its size keeps increasing to support more concurrent threads from generation to generation. Using traditional SRAM-based RFs, there are concerns in both...
A Sub-μ A Stand-By Current Synchronous Electric Charge Extractor for Piezoelectric Energy Harvesting
Aldo Romani, Matteo Filippi, Michele Dini, Marco Tartagni
Article No.: 7
In the field of energy harvesting there is a growing interest in power management circuits with intrinsic sub-μ A current consumptions, in order to operate efficiently with very low levels of available power. In this context, integrated...
Hrishikesh Jayakumar, Arnab Raha, Woo Suk Lee, Vijay Raghunathan
Article No.: 8
Transiently Powered Computers (TPCs) are a new class of batteryless embedded systems that depend solely on energy harvested from external sources for performing computations. Enabling long-running computations on TPCs is a major challenge due to...
Fault-Tolerant Operations for Universal Blind Quantum Computation
Chia-Hung Chien, Rodney Van Meter, Sy-Yen Kuo
Article No.: 9
Blind quantum computation is an appealing use of quantum information technology because it can conceal both the client's data and the algorithm itself from the server. However, problems need to be solved in the practical use of blind quantum...
SCKVdd: A Scalable Clock-Controlled Self-Stabilized Voltage Technique for Low Power CMOS Digital Circuits
Article No.: 10
It has been proposed that small amounts of energy dissipate when transfer through a rising Vdd. In typical power gate circuits, the PMOS transistors (PSW) reduce the leakage of power by shutting off outer Vdd to the idle blocks. We...