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Introduction to: Special Issue on Cross-Layer System Design
Yiyu Shi, Takashi Sato
Article No.: 20
Application-Specific Cross-Layer Optimization Based on Predictive Variable-Latency VLSI Design
Vivek K. De, Andrew B. Kahng, Tanay Karnik, Bao Liu, Milad Maleki, Lu Wang
Article No.: 21
Traditional synchronous VLSI design requires that all computations in a logic stage complete in one clock cycle. This leads to increasingly pessimistic design as technology scaling introduces increasingly significant parametric variations that...
ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors
Milan Patnaik, Chidhambaranathan R, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti
Article No.: 22
With the increase in process variations and diversity in workloads, it is imperative to holistically explore optimization techniques for power and temperature from the circuit layer right up to the compiler/operating system (OS) layer. This...
This article presents our research towards developing novel and fundamental methodologies for data representation using spike-timing-dependent encoding. Time encoding efficiently maps a signal's amplitude information into a spike time sequence...
A Cross-Layer Approach to Measure the Robustness of Integrated Circuits
Martin Barke, Ulf Schlichtmann
Article No.: 24
The demands on system robustness and its immunity against perturbations are getting increasingly important. Nearly everybody has an intuitive understanding of what robustness means, but there is no proper way how to measure robustness of...
A Cross-Layer Approach for Early-Stage Power Grid Design and Optimization
Cheng Zhuo, Houle Gan, Wei-Kai Shih, Alaeddin A. Aydiner
Article No.: 25
Power integrity has become increasingly important for sub-32nm designs. Many prior works have discussed power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the...
REDELF: An Energy-Efficient Deadlock-Free Routing for 3D NoCs with Partial Vertical Connections
Jinho Lee, Kyungsu Kang, Kiyoung Choi
Article No.: 26
3D integrated circuits (3D ICs) using through-silicon vias (TSVs) allow to envision the stacking of dies with different functions and technologies, using as an interconnect backbone a 3D network-on-chip (NoC). However, partial...
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators
Davide Zoni, William Fornaciari
Article No.: 27
Networks-on-chip (NoCs) are a widely recognized viable interconnection paradigm to support the multi-core revolution. One of the major design issues of multicore architectures is still the power, which can no longer be considered mainly due...
gem5-PVT: A Framework for FinFET System Simulation under PVT Variations
Xianmin Chen, Niraj K. Jha
Article No.: 28
FinFET has begun replacing CMOS at the 22nm technology node and beyond. Compared to planar CMOS, FinFET has a higher on-current and lower leakage due to its double-gate structure. A FinFET-based system simulation framework can be very helpful to...
An MINLP Model for Scheduling and Placement of Quantum Circuits with a Heuristic Solution Approach
Tayebeh Bahreini, Naser Mohammadzadeh
Article No.: 29
Recent works on quantum physical design have pushed the scheduling and placement of quantum circuit into their prominent positions. In this article, a mixed integer nonlinear programming model is proposed for the placement and scheduling of...
Maintaining benefits of CMOS technology scaling is becoming challenging, primarily due to increased manufacturing complexities and unwanted passive power dissipations. This is particularly challenging in SRAM, where manufacturing precision and...