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Guest Editors’ Introduction: Hardware and Algorithms for On-Chip Learning
Yu Cao, Xin Li, Taemin Kim, Suyog Gupta
Article No.: 30
SPARCNet: A Hardware Accelerator for Efficient Deployment of Sparse Convolutional Networks
Adam Page, Ali Jafari, Colin Shea, Tinoosh Mohsenin
Article No.: 31
Deep neural networks have been shown to outperform prior state-of-the-art solutions that often relied heavily on hand-engineered feature extraction techniques coupled with simple classification algorithms. In particular, deep convolutional neural...
Structured Pruning of Deep Convolutional Neural Networks
Sajid Anwar, Kyuyeon Hwang, Wonyong Sung
Article No.: 32
Real-time application of deep learning algorithms is often hindered by high computational complexity and frequent memory accesses. Network pruning is a promising technique to solve this problem. However, pruning usually results in irregular...
Energy-Efficient and Improved Image Recognition with Conditional Deep Learning
Priyadarshini Panda, Abhronil Sengupta, Kaushik Roy
Article No.: 33
Deep-learning neural networks have proven to be very successful for a wide range of recognition tasks across modern computing platforms. However, the computational requirements associated with such deep nets can be quite high, and hence their...
Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications
Robert Karam, Somnath Paul, Ruchir Puri, Swarup Bhunia
Article No.: 34
Big Data refers to the growing challenge of turning massive, often unstructured datasets into meaningful, organized, and actionable data. As datasets grow from petabytes to exabytes and beyond, it becomes increasingly difficult to run advanced...
VLSI Architectures for the Restricted Boltzmann Machine
Bo Yuan, Keshab K. Parhi
Article No.: 35
Neural network (NN) systems are widely used in many important applications ranging from computer vision to speech recognition. To date, most NN systems are processed by general processing units like CPUs or GPUs. However, as the sizes of dataset...
The recently emerging resistive random-access memory (RRAM) can provide nonvolatile memory storage but also intrinsic computing for matrix-vector multiplication, which is ideal for the low-power and high-throughput data analytics accelerator...
Stochastic CBRAM-Based Neuromorphic Time Series Prediction System
Cory Merkel, Dhireesha Kudithipudi, Manan Suri, Bryant Wysocki
Article No.: 37
In this research, we present a Conductive-Bridge RAM (CBRAM)-based neuromorphic system which efficiently addresses time series prediction. We propose a new (i) voltage-mode, stochastic, multiweight synapse circuit based on experimental bi-stable...
Section: Special Issue on Hardware and Algorithms for Learning On-a-chip
Editorial for JETC Special Issue on Alternative Computing Systems
Rasit O. Topaloglu, Naveen Verma
Article No.: 38
High-Performance Computing with Quantum Processing Units
Keith A. Britt, Travis S. Humble
Article No.: 39
The prospects of quantum computing have driven efforts to realize fully functional quantum processing units (QPUs). Recent success in developing proof-of-principle QPUs has prompted the question of how to integrate these emerging processors into...
Mobile Unified Memory-Storage Structure Based on Hybrid Non-Volatile Memories
Su-Kyung Yoon, Young-Sun Youn, Kihyun Park, Shin-Dug Kim
Article No.: 40
In mobile computing systems, the limited amount of main memory space leads to page swap operation overhead and data duplication in both main memory and secondary storage. Furthermore, SQLite write operations in mobile devices such as smartphones...
Real-Time SoC Security against Passive Threats Using Crypsis Behavior of Geckos
Krishnendu Guha, Debasri Saha, Amlan Chakrabarti
Article No.: 41
The rapid evolution of the embedded era has witnessed globalization for the design of SoC architectures in the semiconductor design industry. Though issues of cost and stringent marketing deadlines have been resolved in such a methodology, yet the...
Computing Polynomials Using Unipolar Stochastic Logic
Yin Liu, Keshab K. Parhi
Article No.: 42
This article addresses subtraction and polynomial computations using unipolar stochastic logic. Stochastic computing requires simple logic gates, and stochastic logic--based circuits are inherently fault tolerant. Thus, these structures are well...
PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees
Pareesa Ameneh Golnari, Yavuz Yetim, Margaret Martonosi, Yakir Vizel, Sharad Malik
Article No.: 43
With increasing technology scaling and design complexity there are increasing threats from device and circuit failures. This is expected to worsen with post-CMOS devices. Current error-resilient solutions ensure reliability of circuits through...
Design of Approximate Compressors for Multiplication
Anusha Gorantla, Deepa P
Article No.: 44
Approximate computing is a promising technique for energy-efficient Very Large Scale Integration (VLSI) system design. It is best suited for error-resilient applications such as signal processing and multimedia. Approximate computing reduces...
Toward Human-Scale Brain Computing Using 3D Wafer Scale Integration
Arvind Kumar, Zhe Wan, Winfried W. Wilcke, Subramanian S. Iyer
Article No.: 45
The Von Neumann architecture, defined by strict and hierarchical separation of memory and processor, has been a hallmark of conventional computer design since the 1940s. It is becoming increasingly unsuitable for cognitive applications, which...
Sketching Computation with Stochastic Processing Engines
Mohammed Alawad, Mingjie Lin
Article No.: 46
This article explores how to leverage stochastic principles to gracefully exploit partial computation results, hence achieving quality-scalable embedded computing. Our work is inspired by the concept of incremental sketching frequently found in...
As we approach the limits of traditional Moore’s-Law scaling, alternative computing techniques that consume energy more efficiently become attractive. Stochastic computing (SC), as a re-emerging computing technique, is a low-cost and...
Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency
Soheil Salehi, Deliang Fan, Ronald F. Demara
Article No.: 48
Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for...
The non-volatile memory (NVM) has the merits of byte-addressability, fast speed, persistency and low power consumption, which make it attractive to be used as main memory. Commonly, user process dynamically acquires memory through memory...
Phase change memory (PCM) is a promising alternative to Dynamic Random Access Memory (DRAM) as main memory due to its merits of high density and low leakage power. Multi-level Cell (MLC) PCM is more attractive than Single-level Cell (SLC) PCM,...