Emerging Technologies in Computing (JETC)


Editorial Board


Yuan Xie
University of California, Santa Barbara
Department of Electrical and Computer Engineering
5159 Harold Frank Hall
Electrical and Computer Engineering Department
Santa Barbara, CA 93106
United States

Prof. Yuan Xie joined UCSB in Fall 2014 after 11 years with Penn State University (2003-2014). He received B.S. degree from Tsinghua University, and his M.S. and Ph.D. degrees from Electrical Engineering Department, Princeton University. Prior to joining Penn State in 2003, he worked as an Advisory Engineer for IBM Microelectronics Division's Worldwide Design Center. He was also on-leave in 2012-13 to work with AMD Research. He was a recipient of the NSF CAREER award. in 2006. His research interests include VLSI Design, Electronics Design Automation, Computer Architecture, Embedded Systems Design. Specifically, recent research projects he has been involved include EDA tools and architectures for 3D IC design, embedded system synthesis, low power and thermal-aware techniques, robust design techniques related to soft errors and process variation.

    +1 (805) 893-5563       +1 (805) 893-3262  

Associate Editors

David Atienza Alonso
EPFL STI SEL-GE ELG 131 (Bâtiment ELG) Station 11
Lausanne, CH-1015

David Atienza Alonso is associate professor of electrical engineering and director of the Embedded Systems Laboratory (ESL) at the Institute of Electrical Engineering within the School of Engineering (STI) of EPFL, Switzerland. Previously he was associate professor at the Computer Architecture and Automation Department of Complutense University of Madrid (UCM), Spain. He received his M.Sc. and Ph.D. degrees in Computer Science from Complutense University, Madrid, Spain, and Inter-University Micro-Electronics Center (IMEC), Leuven, Belgium, in 2001 and 2005, respectively. His research interests focus on system-level design methodologies for high-performance multi-processor systems-on-chip (MPSoC) and low-power embedded systems, including new thermal-aware design for 2D and 3D MPSoCs, design methods and architectures for wireless body sensor networks, dynamic memory management and interconnection hierarchy optimizations. In these fields, he is co-author of more than 200 publications in prestigious journals and international conferences, several book chapters and five U.S. patents. He is the recipient of the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award (ONFA) in 2012 and an External Research Faculty Award of Oracle in 2011 in the area of stable global thermal-aware control for enterprise computer servers. He has served as a Distinguished Lecturer (2014-2015) of the IEEE CASS. He is Senior Member of ACM, and IEEE Fellow.

     +41 21 69 31131       +41 21 69 31132  

Yiran Chen
University of Pittsburgh
Department of Electrical and Computer Engineering
842 Benedum Hall
3700 O'Hara Street
Pittsburgh, PA 15261
United States

Dr. Yiran Chen received B.S. and M.S. (both with honors) in EE from Tsinghua University, China and Ph.D. in ECE from Purdue University, West Lafayette, Indiana. Before he joined University of Pittsburgh in 2010, he worked with Synopsys and Seagate for five years. His research interests include VLSI design, nano-electronic devices and embedded systems. He has published more than 100 technical publications, has 50+ granted US patents and other 20+ pending applications. He coauthored one book 'Nonvolatile Memory Design: Magnetic, Resistive, and Phase Changing', as well as other several book chapters. He is the associate editor or editor of several international journals, such as TCAD, JETC, JCIT etc. He served as technical and organizational committees of more than 20 conferences. He was sitting on the patent review board member of Seagate memory product group in 2007-2010. Dr. Chen received 'The hot 100 products of 2006' from EDN, 'EDN 100 Hot Products Distinction' from Synopsys and the finalist of 'Prestigious 2007 DesignVision Awards' from IEC. His works also received two best paper awards from ISQED 2008 and ISLPED 2010, respectively, and were nominated as the best paper candidates in ISQED, DATE, and ASPDAC for multiple times. He is one of the inventors of 'Spintronic Memristor'.

    +1 (412) 624-5836       +1 (412) 624-8003  

Rolf Drechsler
University of Bremen
Group of Computer Architecture
University of Bremen/DFKI
Bibliothekstrasse 1 (MZH)
Bremen, 28359

Rolf Drechsler received the Diploma and Dr. Phil. Nat. degrees in computer science from J.W. Goethe University Frankfurt am Main, Frankfurt am Main, Germany, in 1992 and 1995, respectively. He was with the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and with the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since October 2001, he has been with the University of Bremen, Bremen, Germany, where he is currently a Full Professor and the Head of the Group for Computer Architecture, Institute of Computer Science. In 2011, he additionally became the Director of the Cyber-Physical Systems group at the German Research Center for Artificial Intelligence (DFKI) in Bremen. His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design.

Rolf Drechsler was a member of Program Committees of numerous conferences including e.g., DAC, ICCAD, DATE, ASP-DAC, FDL, MEMOCODE, FMCAD, Symposiums Chair ISMVL 1999 and 2014, and the Topic Chair for 'Formal Verification' DATE 2004, DATE 2005, DAC 2010, as well as DAC 2011. He is a co-founder of the Graduate School of Embedded Systems and he is the coordinator of the Graduate School 'System Design' funded within the German Excellence Initiative. He received best paper awards at the Haifa Verification Conference (HVC) in 2006, the Forum on specification & Design Languages (FDL) in 2007 and 2010, the IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) in 2010 and the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in 2013. In addition to serving as Associate Editor for JETC, he also serves as an Associate Editor for IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

    +49 421 218 63932       +49 421 218 7385  

Tsung-Yi Ho
National Tsing Hua University, Taiwan
Department of Computer Science
National Tsing Hua University
No. 101, Sec.2, Kuang-Fu Rd.
Hsinchu, 30013

Tsung-Yi Ho received his Ph.D. in Electrical Engineering from National Taiwan University in 2005. He is a Professor with the Department of Computer Science of National Tsing Hua University, Hsinchu, Taiwan. His research interests include design automation and test for microfluidic biochips and nanometer integrated circuits. He has presented 9 tutorials and contributed 9 special sessions in ACM/IEEE conferences, all in design automation for microfluidic biochips. He has been the recipient of the Invitational Fellowship of the Japan Society for the Promotion of Science (JSPS), the Humboldt Research Fellowship by the Alexander von Humboldt Foundation, and the Hans Fischer Fellow by the Institute of Advanced Study of the Technical University of Munich. He was a recipient of the Best Paper Awards at the VLSI Test Symposium (VTS) in 2013 and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2015. He served as a Distinguished Visitor of the IEEE Computer Society for 2013-2015, the Chair of the IEEE Computer Society Tainan Chapter for 2013-2015, and the Chair of the ACM SIGDA Taiwan Chapter for 2014-2015. Currently he serves as an ACM Distinguished Speaker, a Distinguished Lecturer of the IEEE Circuits and Systems Society, and Associate Editor of the ACM Journal on Emerging Technologies in Computing Systems, ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and IEEE Transactions on Very Large Scale Integration Systems, Guest Editor of IEEE Design & Test of Computers, and the Technical Program Committees of major conferences.

    +886 (3) 5731214        +886 (3) 5731201   

Ramesh Karri
Polytechnic Institute of New York University
Department of Electrical and Computer Engineering
Polytechnic Institute of New York University
6 Metrotech Center
Brooklyn, NY 11201
United States

Ramesh Karri is a Professor of Electrical and Computer Engineering at Polytechnic Institute of New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research interests include trustworthy ICs and processors; High assurance nanoscale IC architectures and systems; VLSI Design and Test; Interaction between security and reliability.

He has over 150 journal and conference publications in these areas. He has written two invited articles in IEEE Computer on Trustworthy Hardware, an invited article on Digital Logic Design using Memristors in Proceedings of IEEE and an Invited article in IEEE Computer on Reliable Nanoscale Systems. These will be the basis of the Lectures that he plans to offer. He was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He served on the 2006 DARPA ISAT study on 'Trust in Integrated Circuits'. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Hardware security lead of the Center for research in interdisciplinary studies in security and privacy -CRISSP (, co-founder of the Trust-Hub ( and organizes the annual red team blue team event at NYU, the Embedded Systems Challenge ( He cofounded and served as the chair of the IEEE Computer Society Technical Committee on Nanoscale architectures. He is a cofounder and steering committee member of the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He is the Program Chair (2012) and General Chair (2013) of IEEE Symposium on Hardware Oriented Security and Trust (HOST). He is the Program Co-Chair (2012) and General Co-Chair (2013) of IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems. He is the General Chair of the 2013 NANOARCH. He serves on several program committees. He is the Associate Editor of IEEE Transactions on Information Forensics and Security and Associate Editor of ACM Journal on Emerging Computing Technologies.

He has organized invited tutorials on various aspects of Trustworthy Hardware (including at 2012 VLSI Test Symposium, 2012 International Conference on Computer Design, 2013 IEEE North Atlantic Test Workshop, 2013 Design Automation and Test in Europe). He currently advises eight PhD students and mentors two postdoctoral candidates. His research is funded by NSF (IGERT, Scholarship for Service, Capacity Building, CRI, Cybersecurity), DOE (GAANN), AFRL, ARO, Cisco and Intel. He organizes the annual Embedded Systems Challenge to promote a challenges-based approach to hardware trust validation and embedded systems education.

    +1 (718) 260-4011   

Eren Kursun
Columbia University
1214 Amsterdam Avenue
New York, New York 10027
United States

Eren Kursun is an Adjunct Professor and Director at Columbia University. She received her B.Sc. in Electrical and Electronics from Bogazici University and her M.Sc. and Ph.D. degrees in Computer Science from University of California. Prior to her role at Columbia she served as a Program Director for Research and Innovation at JPMorgan and Research Program Manager/Executive Staff to CIO at IBM Corporate Headquarters. Dr. Kursun received number of IBM Outstanding Research and Technical Accomplishment Awards, as well as Invention and High-Value Patent Awards for her research work. She received the Best Paper Award at IEEE International Symposium on Low Power Design and IEEE International Conference in Computer Design. Dr. Kursun is currently serving as an Associate Editor for IEEE and ACM Journals such as IEEE Transactions on Emerging Technologies in Computing, and IEEE Transactions on Computers, IEEE TC.


Saraju P. Mojanty
University of North Texas

Denton, Texas
United States

Saraju P. Mohanty is Professor at the Department of Computer Science and Engineering (CSE), University of North Texas (UNT), where he directs the NanoSystem Design Laboratory (NSDL). He obtained a Ph.D. in Computer Engineering from the University of South Florida (USF) in 2003, a Master’s degree in Systems Science and Automation (SSA) from the Indian Institute of Science (IISc), Bangalore, India in 1999, and a Bachelor's degree (Honors) in Electrical Engineering from Orissa University of Agriculture and Technology (OUAT), Bhubaneswar, India in 1995. Prof. Mohanty's research is in 'Low-Power High-Performance Secure Electronic Systems'. Prof. Mohanty's research has been funded by the National Science Foundation (NSF), the Semiconductor Research Corporation (SRC), and the USA Air Force. Dr. Mohanty is an inventor of 4 USA patents. Prof. Mohanty is an author of 200 peer-reviewed research articles and 3 books. The publications are well-received by the world-wide peers with a total of 2,300 citations leading to an h-index of 24 and i10-index of 62 (from Google Scholar). His latest book titled Nanoelectronic Mixed-Signal System Design is published by McGraw-Hill in 2015 is a best seller. This book received the 2016 PROSE (Professional & Scholarly Excellence) Award for best textbook in physical sciences and mathematics from the Association of American Publishers. Prof. Mohanty currently serves as the Chair of Technical Committee on Very Large Scale Integration (TCVLSI), IEEE Computer Society (IEEE-CS). He has been serving on the editorial board of several peer-reviewed international journals and magazines. He currently serves on the editorial board of 5 peer-reviewed international journals including IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), IET Circuits, Devices & Systems Journal, and IEEE Consumer Electronics Magazine. He has been serving as a guest editor for dozens of prestigious journals including ACM Journal on Emerging Technologies in Computing Systems (JETC) and IEEE Transactions on Emerging Topics in Computing (TETC). He serves on the organizing and program committee of several international conferences. He was a conference chair for IEEE-CS Symposium on VLSI (ISVLSI) 2012 and 2014 and founder conference chair for IEEE International Symposium on Nanoelectronic and Information Systems (IEEE-iNIS) in 2015. Prof. Mohanty is a senior member of IEEE and ACM. Prof. Mohanty has supervised 7 Ph.D. dissertations and 24 M.S. theses. Eight of these advisees have received outstanding student awards at UNT. He has received Honors Day recognition as an inspirational faculty at the UNT for multiple years. He has also received UNT Provost’s Thank a Teacher recognition for multiple years. He is a senior member of IEEE and ACM.


Michael Niemier
University of Notre Dame
380 Fitzpatrick Hall
Notre Dame, Indiana 46556
United States

Michael T. Niemier is currently an Associate Professor at the University of Notre Dame. His research interests include designing, facilitating, and evaluating circuits and architectures based on emerging technologies. Currently, Niemier's research efforts are based on both spin devices, as well as new transistor technologies. Work on the latter is being conducted under the umbrella of the DARPA/SRC STARnet center LEAST. He is the recipient of an IBM Faculty Award, a university wide award for excellence in undergraduate teaching at the University of Notre Dame, and the best paper award at the IEEE Symposium on Nanoscale Architectures (2009). Niemier has served on numerous technical program committees for design related conferences (including DAC, DATE, ICCAD etc.), and also has served/is serving as the chair of the emerging technologies track at DATE and DAC.

    +1 (574) 631-3858   

Steven Nowick
Columbia University, USA
Department of Computer Science
Columbia University
508 Computer Science Building; Mail Code: 0401
1214 Amsterdam Avenue
New York, NY 10027
United States

Steven M. Nowick is a Professor of Computer Science and Electrical Engineering at Columbia University, and Chair of the Computer Engineering Program. He received a Ph.D. in Computer Science from Stanford University in 1993, and a B.A. from Yale University. His research interests include asynchronous and mixed-timing circuits, computer-aided digital design, networks-on-chip, high-performance digital systems, logic synthesis, and ultra-low-energy systems.

Dr. Nowick received an NSF Faculty Early Career (CAREER) Award (1995), an Alfred P. Sloan Research Fellowship (1995) and an NSF Research Initiation Award (RIA) (1993). He is also a Fellow of the IEEE (2009). He received Best Paper Awards at the International Conference on Computer Design (1991 and 2012) and the IEEE Async Symposium (2000).

Dr. Nowick co-founded the IEEE 'Async' Symposia series and was Program Committee Co-Chair (1994, 1999) and General Co-Chair (2005).

He was also Program Chair of the 2002 IEEE/ACM International Workshop on Logic and Synthesis [IWLS].

He has served as a track and subcommittee chair for the program committees of several leading conferences: Design Automation Conference [DAC] (2011-2013), Design, Automation and Test in Europe [DATE] (2009-2010), and International Conference on Computer Design [ICCD] (2005). He was also a Guest Editor of a special issue of the journal, Proceedings of the IEEE, on asynchronous design (1999). He served as associate editor of IEEE Transactions on Computer-Aided Design (2003-2011) and IEEE Transactions on VLSI Systems (2001-2007). He is currently chair of the ACM/SIGDA 'Outstanding PhD Dissertation in EDA Award' committee (2012-2013). He holds 10 issued US patents.

    +1 (212) 939-7056       +1 (212) 666-0140  

Partha Pande
Washington State University, USA
School of Electrical Engineering & Computer Science
Washington State University
PO BOX 642752
Pullman, WA 99164-2752
United States

Partha Pratim Pande received the M.S degree in computer science from the National University of Singapore and the Ph.D. degree in electrical and computer engineering from the University of British Columbia, Vancouver, BC, Canada. He is an Associate Professor and the holder of the Boeing Centennial chair in Computer Engineering in the School of Electrical Engineering and Computer Science, Washington State University, Pullman.

His current research interests are novel interconnect architectures for multicore chips, on-chip wireless communication networks, and hardware accelerators for biocomputing. Partha currently serves on the Editorial Board of IEEE Design and Test and Sustainable Computing: Informatics and Systems. He also serves in the program committee of many reputed international conferences. He has won the NSF CAREER award for his research on Wireless Network on Chip in 2009. He is a senior member of IEEE.

    +1 (509) 335-5223       +1 (509) 335-3818  

Yiyu Shi
University of Notre Dame, USA
Dept. of Computer Science and Engineering
The University of Notre Dame
South Bend, IN 46556-5659
United States

Yiyu Shi received his B.S. degree (with honors) in Electronic Engineering from Tsinghua University, Beijing, China in 2005, the M.S and Ph.D. degree in Electrical Engineering from the University of California, Los Angeles in 2007 and 2009 respectively. He was with the Electrical and Computer Engineering Department at Carnegie Mellon University from Dec 2009 to April 2010, with the Electrical and Computer Engineering Department at Missouri University of Science and Technology from 2010 to 2015. Since 2015, he has been with the University of Notre Dame, where he is currently an associate professor in the Computer Science and Engineering Department. His current research interests include three-dimensional integrated circuits, hardware security and renewable energy applications.

In recognition of his research, seven of his papers have been nominated for the Best Paper Award and one paper have received the Best Paper in Track, all in top conferences (DAC'05, ICCAD'07, ICCD'08, ASPDAC'09, DAC'09, ISPD'13, ICCAD'14, ISPD'15). He was also the recipient of IBM Invention Achievement Award in 2009, Japan Society for the Promotion of Science (JSPS) Faculty Invitation Fellowship, Humboldt Research Fellowship for Experienced Researchers, IEEE St. Louis Section Outstanding Educator Award, Academy of Science (St. Louis) Innovation Award, Missouri S&T Faculty Excellence Award, National Science Foundation CAREER Award, IEEE Region 5 Outstanding Individual Achievement Award, all in 2014, and the Air Force Summer Faculty Fellowship in 2015. He has served on the technical program committee of many international conferences including DAC, ICCAD, ISPD, ASPDAC and ICCD. He is a senior member of IEEE.

    +1 (574) 631-8321       +1 (574) 631-9260  

Dmitri Strukov
University of California, Santa Barbara
Electrical and Computer Engineering 9560
Santa Barbara, California 93106
United States

Dmitri Strukov is an Associate Professor of Electrical and Computer Engineering at University of California at Santa Barbara. Prior to joining UCSB Dmitri worked as a postdoctoral associate, first at Stony Brook University (Aug. 2006 – Dec. 2007), and then at Hewlett Packard Laboratories (Jan. 2007 – Jun. 2009) on various aspects of nanoelectronic systems. He received a MS in applied physics and mathematics from the Moscow Institute of Physics and Technology in 1999 and a PhD in electrical engineering from Stony Brook University in New York in 2006. He is a member of ACM, MRS, and IEEE societies. Dmitri’s research broadly concerns different aspects of computation, in particular addressing questions on how to efficiently perform computation on various levels of abstraction. His current research focus is on hardware implementations of artificial neural networks with emerging memory devices.

    +1 (805) 893-2971       +1 (805) 893-3262  

Guangyu Sun
Peking University
515S Science Building #5
Peking University
5 Yiheyuan Road
Beijing, 100871

Dr. Guangyu Sun is a faculty member at the Center for Energy-efficient Computing and Applications (CECA) at Peking University. He received his B.S. and M.S degrees from Tsinghua University, Beijing, in 2003 and 2006, respectively. He received his Ph.D. degree in Computer Science from the Pennsylvania State University in 2011. Dr. Sun received the 2012 EDAA outstanding dissertation award for his Ph.D. thesis titled “Exploring Memory Hierarchy Design with Emerging Memory Technologies”. His research interests include computer architecture and computer systems. He has published 40+ journals and refereed conference papers in these areas with a focus on emerging memory/storage architectures and systems. Dr. Sun is an active volunteer in the communities of computer architecture, VLSI, and design automation. He has been serving as a program committee member and track chair for several conferences in these areas, including DATE, ASP-DAC, GLSVLSI, VLSID, and NAS. He is serving as the local arrangement chair and in TPC for ISLPED 2013. He has also served as a peer reviewer and technical referee for several journals, which include IEEE Micro, IEEE TVLSI, IEEE TCAD, etc. Guangyu Sun is a member of CCF, IEEE, and ACM.


Jeffrey Vetter
Oak Ridge National Laboratory & Georgia Tech
Oak Ridge National Laboratory
One Bethel Valley Road
Oak Ridge , Tennessee 37831-6173
United States

Jeffrey Vetter, Ph.D., is a Distinguished R&D Staff Member at Oak Ridge National Laboratory (ORNL). At ORNL, Vetter is the founding group leader of the Future Technologies Group in the Computer Science and Mathematics Division. Vetter also holds joint appointments at the Georgia Institute of Technology and the University of Tennessee-Knoxville. Vetter earned his Ph.D. in Computer Science from the Georgia Institute of Technology. He joined ORNL in 2003, after stints as a computer scientist and project leader at Lawrence Livermore National Laboratory, and postdoctoral researcher at the University of Illinois at Urbana-Champaign. Currently, Vetter's research investigates the design of next-generation extreme-scale HPC architectures, including non-volatile memory systems, heterogeneous multicore processors, and field-programmable gate arrays (FPGAs), for extreme scale applications. Vetter is a Senior Member of the IEEE, and a Distinguished Scientist Member of the ACM. In 2010, Vetter, as part of an interdisciplinary team from Georgia Tech, NYU, and ORNL, was awarded the ACM Gordon Bell Prize . Also, his work has won awards at major conferences including Best Paper Awards at the International Parallel and Distributed Processing Symposium (IPDPS) and EuroPar, Best Student Paper Finalist at SC14, and Best Presentation at EASC 2015. His recent books, entitled "Contemporary High Performance Computing: From Petascale toward Exascale (Vols. 1 and 2)," survey the international landscape of HPC.


Wei Zhang
Hong-Kong University of Science and Technology
Room 2419
Hong Kong University of SCience and Technology
Hong Kong,

Wei Zhang received the B.S and M.S degrees from Harbin Institute of Technology, Harbin, China, in 1999 and 2001, respectively, and the Ph.D. degree from Princeton University, Princeton, NJ, USA in 2009. She is currently an Assistant Professor with the Department of Electronic and Computer Engineering, the Hong Kong University of Science and Technology, Hong Kong, where she established the Reconfigurable System Laboratory. She was an Assistant Professor with the School of Computer Engineering, Nanyang Technological University, Singapore, from 2010 to 2013. She was a Co-Investigator of Singapore-MIT Alliance for Research and Technology and a collaborator with the ASTAR-UIUC Advanced Digital Sciences Center on low power electronics and field-programmable gate array (FPGA) accelerated computing. She authored over 60 technical papers in referred international journals and conferences, and authored three book chapters. Her current research interests include reconfigurable system, power and thermal management, embedded system security, and emerging technologies. Dr. Zhang received the Best Paper Award from the IEEE Computer Society Annual Symposium on VLSI. She received the Wu Prize for research excellence from Princeton University. She currently serves as an Area Editor of Reconfigurable Computing for ACM Transactions on Embedded Computing Systems, and an Associate Editor of IEEE Transaction on Very Large Scale Integration Systems. She also serves on many Organization Committees and Technical Program Committees, including Design Automation Conference, Conference on Compliers, Architectures and Synthesis of Embedded Systems, the Asia and South Pacific Design Automation Conference, the International Conference on Embedded and Real-Time Computing Systems and Applications, the International Conference on Field Programmable Logic and Applications, and the International Conference on Field-Programmable Technology, etc.

    +852 2358-8170  

Information Director

Theocharis (Theo) Theocharides
University of Cyprus
Dept. of Electrical and Computer Engineering, University of Cyprus
75 Kallipoleos Avenue
P.O.Box 20537
Nicosia, 1678

Theocharis (Theo) Theocharides holds a Ph.D. degree in Computer Science and Engineering from the Pennsylvania State University. He is currently an Assistant Professor at the Department of Electrical and Computer Engineering, at the University of Cyprus. His research focuses on the broad area of intelligent embedded systems design, with emphasis on domain-specific architectures and design of reliable and low power embedded and application specific processors. He directs the Embedded and Application-Specific System-on-Chip Lab at the KIOS Research Centre for Intelligent Systems and Networks, which currently runs several on-going projects related to embedded and mobile processors, embedded computer vision, embedded pattern recognition and classification architectures, and intelligent system-level monitoring and dynamic reconfiguration for performance, energy and reliability of Systems-on-Chip. He has authored/co-authored more than 50 papers in internationally acclaimed scientific journals and conferences. He is a senior member of the IEEE and the IEEE Computer Society, and currently serves as the Information Director of the ACM Journal on Emerging Technologies in Computing Systems, the IEEE Design and Test of Computers magazine, and on several Organizational and Technical Program Committee boards of various IEEE/ACM Conferences.

    +357 22892259        +357 22892260  

Journal Administrator

Genesis Codina
University of California, Santa Barbara

Santa Barbara, California 93106
United States

ACM Journals Manager

Laura Lander
2 Penn Plaza, Suite 701
New York, NY 10121-0701
United States
    +1 212-626 0665  

Past Editors-in-Chief

Krishnendu Chakrabarty
Duke University
Department of Electrical and Computer Engineering
Duke University
Box 90291, 130 Hudson Hall
Durham, NC 27708
United States

Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, and the M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now the William H. Younger Distinguished Professor of Engineering in the Department of Electrical and Computer Engineering at Duke University. He is also the Executive Director of Graduate Studies and a Professor of Computer Science. His current research interests include: testing and design-for-testability of SOC and 3D integrated circuits; digital microfluidics, biochips, and cyberphysical system integration; enterprise system optimization. Prof. Chakrabarty is a Fellow of ACM, a Fellow of IEEE, and a Golden Core Member of the IEEE Computer Society. He is a recipient of the Humboldt Research Award. In addition to serving as EIC for JETC, he serves as an Associate Editor of IEEE Transactions on Computers and IEEE Transactions on Biomedical Circuits and Systems.

    +1 (919) 660-5244       +1 (919) 660-5293  

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