ACM Journal on

Emerging Technologies in Computing (JETC)

Latest Articles

Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics

Artificial Neural Network computation relies on intensive vector-matrix multiplications. Recently,... (more)

Energy-Efficient Neural Computing with Approximate Multipliers

Neural networks, with their remarkable ability to derive meaning from a large volume of complicated or imprecise data, can be used to extract patterns... (more)

Real-Time and Low-Power Streaming Source Separation Using Markov Random Field

Machine learning (ML) has revolutionized a wide range of recognition tasks, ranging from text analysis to speech to vision, most notably in cloud... (more)

A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks

FPGA-based hardware accelerators for convolutional neural networks (CNNs) have received attention due to their higher energy efficiency than GPUs.... (more)

A Study of Complex Deep Learning Networks on High-Performance, Neuromorphic, and Quantum Computers

Current deep learning approaches have been very successful using convolutional neural networks trained on large graphical-processing-unit-based... (more)

Silicon Photonics for Computing Systems

A Learning-Based Thermal-Sensitive Power Optimization Approach for Optical NoCs

Optical networks-on-chip (NoCs) based on silicon photonics have been proposed as emerging on-chip communication architectures for chip multiprocessors... (more)

A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network

Nanophotonic networks, a potential candidate for future networks on-chip, have been challenged for their reliability due to several device-level... (more)

Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping

To face the complex communication problems that arise as the number of on-chip components grows up, photonic networks-on-chip (NoCs) have been... (more)


About JETC

The Journal of Emerging Technologies in Computing Systems invites submissions of original technical papers describing research and development in emerging technologies in computing systems. Major economic and technical challenges are expected to impede the continued scaling of semiconductor devices. This has resulted in the search for alternate mechanical, biological/biochemical, nanoscale electronic, asynchronous and quantum computing and sensor technologies. 

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IMFlexCom: Energy Efficient In-memory Flexible Computing using Dual-mode SOT-MRAM

In this paper, we propose an In-Memory Flexible Computing platform (IMFlexCom) using a novel Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array architecture, which could work in dual mode: memory mode- to work as non-volatile memory and computing mode- to implement re-configurable logic (AND/OR/XOR) within the memory array. Such intrinsic in-memory logic could be used to process data within memory to greatly reduce power-hungry and long distance massive data communication in conventional Von-Neumann computing systems. We further employ bulk bitwise vector operation and data encryption engine with Advanced Encryption Standard (AES) as case studies to investigate the performance of our proposed in-memory computing architecture. Our design shows < 35× energy saving and < 18× speedup for bulk bitwise in-memory vector AND/OR operation compared to DRAM based in-memory logic. Again, our proposed design can achieve 77.27% and 85.4% lower energy consumption compared to CMOS-ASIC and CMOL based AES implementations, respectively. It offers almost similar energy consumption as recent DW-AES implementation with 66.7% less area overhead.

Hardware Trojan Detection Using the Order of Path Delay

Many fabrication-less design houses are outsourcing their designs to third party foundries for fabrication to lower cost. This IC development process, however, raises serious security concerns on Hardware Trojans (HTs). In this paper, for the first time, we propose a two-phase technique, which uses the order of the path delay in path pairs to detect HTs. In the design phase, a full-cover path set that covers all the nets of the design is generated; meanwhile in the set, the relative order of paths in path pairs is determined according to their delay. The order of the paths in path pairs serves as the fingerprint of the design. In the test phase, the actual delay of the paths in the full-cover set is extracted from the fabricated circuits, and the order of paths in path pairs is compared with the fingerprint generated in the design phase. A mismatch between them indicates the existence of Trojans circuits. Both process variations and measurement noise are taken into consideration. The efficiency and accuracy of the proposed technique are confirmed by a series of experiments including the examination of both violated path pairs incurred by HTs and their false alarm rate.

Design and Multi-Abstraction Level Evaluation of a NoC Router for Mixed-Criticality Real-Time Systems

A Mixed Criticality System (MCS) combines real-time software tasks with different criticality levels. In a MCS, the criticality level specifies the level of assurance against system failure. For high-critical flows of messages, it is imperative to meet deadlines, otherwise the whole system might fail, leading to catastrophic results, like, loss of life or serious damage to the environment. In contrast, low-critical flows may tolerate some delays. Furthermore, in MCS, flow performances such as the Worst Case Communication Time (WCCT) may vary depending on the criticality level of the applications. Then, execution platforms must provide different operating modes for applications with different levels of criticality. To conclude, in Network-On-Chip (NoC), sharing resources between communication flows can lead to unpredictable latencies and subsequently turns the implementation of MCS in many-core architectures challenging. In this article, we propose and evaluate a new NoC router to support MCS based on an accurate WCCT analysis for high-critical flows. The proposed router, called \textbf{DAS} (\textbf{D}ouble \textbf{A}rbiter and \textbf{S}witching router), jointly uses {\it Wormhole} and {\it Store And Forward} communication techniques for low and high-critical flows respectively. It ensures that high-critical flows meet their deadlines while maximizing the bandwidth remaining for the low-critical flows.

T-count and Qubit Optimized Quantum Circuit Design of the Non-Restoring Square Root Algorithm

Quantum circuits for basic mathematical functions such as the square root are required to implement scientific computing algorithms on quantum computers. Quantum circuits that are based on Clifford+T gates can be made fault tolerant in nature but the T gate is very costly to implement. As a result. reducing T-count has become an important optimization goal. Further, quantum circuits with many qubits are difficult to realize making designs that save qubits and produce no garbage outputs desirable. In this work, we present a T-count optimized quantum square root circuit with only 2·n+1 qubits and no garbage output. To have fair comparison against existing work, the Bennetts garbage removal scheme is used to remove garbage output from existing works. We determined that the proposed design achieves an average T-count savings of 40.91%, 98.88%, 39.25% and 26.11% as well as qubit savings of 85.46%, 95.16%, 90.59% and 86.77% compared to existing work.

STDP-based Unsupervised Feature Learning using Convolution-over-time in Spiking Neural Networks for Energy-Efficient Neuromorphic Computing

Brain-inspired learning models attempt to mimic the computations performed in the neurons and synapses constituting the human brain to achieve its efficiency in cognitive tasks. In this work, we propose spike timing dependent plasticity based unsupervised feature learning in Convolutional Spiking Neural Network (SNN). We use shared weight kernels that are trained to encode representative features underlying the input patterns, thereby improving the sparsity as well as the robustness of the learning model. We show that the proposed Convolutional SNN self-learns several visual categories for object recognition with fewer training patterns than the traditional fully-connected SNN while yielding competitive accuracy. Further, we present an energy-efficient implementation of the Convolutional SNN using a crossbar array of spintronic synapses. Our system-level simulation indicates that the Convolutional SNN offers up to 9.3× reduction in the energy consumption per training pattern compared to the fully-connected SNN.

Semi-Trained Memristive Crossbar Computing Engine with In-Situ Learning Accelerator

On-device learning has gained a significant attention recently as it offers local data processing which ensures user privacy and low power consumption especially on mobile devices and energy constrained platforms. This paper proposes on-device training circuitry for threshold-current memristors integrated in crossbar structure. Furthermore, this paper investigates alternate approaches of mapping the synaptic weights to memristive crossbar, thereby realizing a simplified neuromemristive system. The proposed design is studied within the context of extreme learning machine (ELM) while using delta rule learning algorithm to train the output layer. The network is implemented using IBM 65nm technology node and verified in Cadence Spectre environment. The hardware model is verified for classification with binary and multi-class datasets. The total power for a single 4x4 layer network is estimated to be ~29.62uW, while the area is estimated to be 26.48um x 22.35um.

DFR: An Energy-efficient Analog Delay Feedback Reservoir Computing System for Brain-inspired Computing

Confronting the explosive escalation of data density, von Neumann computing systems, which compute and store data in separated locations, have reached its computational bottleneck. As the emerging computing paradigm, the reservoir computing system is inspired by the working mechanism of mammalian brains; it has proven its benefit to multifaceted applications. In this work, we successfully designed and fabricated an energy efficient analog delayed feedback reservoir (DFR) computing system, which is embedded with a temporal encoding scheme, a nonlinear transfer function, and a dynamic delayed feedback loop. Measurement results demonstrate its high energy efficiency with rich dynamic behaviors, whereby the working mechanism has closely mimicked the behavior of biological neurons. The system performance, as well as the robustness, are studied and analyzed through the Monte-Carlo simulation. The proposed DFR computing system conceptually evolves its training mechanism and computing architecture; such system is capable of nonlinearly projecting input patterns onto higher dimensional spaces for the future classification while operating at the edge of chaos region with merely 526¼W of power consumption. To the best of our knowledge, our work represents the first analog integrated circuit (IC) implementation of the DFR computing system.

Efficient Hardware Implementation of Cellular Neural Networks with Incremental Quantization and Early Exit

Cellular neural networks (CeNNs) have been widely adopted in image processing tasks. Recently,various hardware implementations of CeNNs have emerged in the literature, with FPGA being one of the most popular choices due to its high exibility and low time-to-market. However, CeNNs typically involve extensive computations in a recursive manner. As an example, to simply process an image of 1920x1080 pixels requires 4-8 Giga oating point multiplications, which needs to be done in a timely manner for real-time applications. To address this issue, in this paper we propose a compressed CeNN framework for efcient FPGA implementations. It involves various techniques such as incremental quantization and early exit, which signifcantly reduces computation demands while maintaining an acceptable performance. While similar concept has been explored in hardware implementations of Convolutional Neural Networks (CNNs), CeNNs have completely dierent computation patterns which require dierent quantization and implementation strategies. Experimental results on FPGAs show that incremental quantization and early exit can achieve a speedup of up to 7.8x and 8.3x, respectively, compared with the state-of-the-art implementations, while with almost no performance loss with four widely-adopted applications. We also discover that dierent from CNNs, the optimal quantization strategies of CeNNs depend heavily on the applications.

Efficient Memristor based Architecture for Intrusion Detection and High Speed Packet Classification

Deep packet inspection (DPI) is a critical component to prevent intrusion detection. This requires a detailed analysis of each network packet header and body. Although this is often done on dedicated high power servers in most networked systems, mobile systems could potentially be vulerable to attack if utilized on an unprotected network. In this case having DPI hardware on the mobile system would be highly beneficial. Unfortunately, DPI hardware is generally area and power consuming making them difficult to implement in mobile systems. We developed a memristor crossbar based approach, inspired by memristor crossbar neuromorphic circuits, for a low power, low area, and high throughput DPI system that examines both the header and body of a packet. Two key types of circuits are presented: static pattern matching and regular expression circuits. This system is able to reduce execution time and power consumption due to its high density grid and massive parallelism. Independent searches are performed using a low power memristor crossbar arrays giving rise to a throughput of 390Gbps for minimum size packets (40B long) with no loss in the classification accuracy. The memristor crossbar does not consume static power and consumes dynamic power of 0.00336mW per Snort header rule.

Design Space Exploration of 3D Network-on-Chip: A Sensitivity-based Optimization Approach

High-performance and energy-efficient Network-on-Chip (NoC) architecture is one of the crucial components of the manycore processing platforms. A very promising NoC architecture recently proposed in the literature is the three-dimensional small-world NoC (3D SWNoC). Due to short vertical links in 3D integration and the robustness of small-world networks, the 3D SWNoC architecture outperforms its other 3D counterparts. However, the performance of 3D SWNoC is highly dependent on the placement of the links and associated routers. In this paper, we propose a sensitivity-based link placement algorithm (SEN) to optimize the performance of 3D SWNoC.We compare the performance of SEN algorithm with simulated annealing- (SA) and recently proposed machine learning-based (ML) optimization algorithm. The optimized 3D SWNoC obtained by the proposed SEN algorithm achieves, on average, 11.5% and 13.6% lower latency and 18.4% and 21.7% lower energy-delay product than those optimized by the SA and ML algorithms respectively. In addition, the SEN algorithm is 26 to 33 times faster than the SA algorithm for the optimization of 64-, 128-, and 256-core 3D SWNoC designs.However, we find that ML-based methodology has faster convergence time than SEN and SA for bigger systems.

Sparse hardware embedding of spiking neuron systems for community detection

Adapting deep neural networks and deep learning algorithms for neuromorphic hardware has been well established for discriminative and generative models. We study the applicability of neural networks and neuromorphic hardware for solving general optimization problems without the use of adaptive training or learning algorithms. We leverage the dynamics of Hopfield networks and spin glass systems to construct a fully connected spiking neural system to generate synchronous spike responses indicative of the underlying community structure in an undirected, unweighted graph. Mapping this fully connected system to current neuromorphic hardware is done by embedding sparse tree graphs to generate only the leading order spiking dynamics. We demonstrate that for a chosen set of benchmark graphs, non-overlapping communities can be identified, even with the loss of higher order spiking behavior.

Thermal-aware Test Scheduling Strategy for Network-on-Chip based Systems

Rapid progress in technology scaling makes transistors smaller and faster over successive generations, and consequently core count in a system gets increased, in which a flexible and scalable packet-switched architecture---Network-on-Chip (NoC)---is commonly used for communication among the cores. To test such system, NoC is reused as a test delivery mechanism. This work proposes a preemptive test scheduling technique for NoC based system to reduce the testtime by minimizing the network resource conflicts. The preemptive test scheduling problem has been formulated using Integer Linear Programming (ILP). Thermal safety during testing is an utmost challenging problem, particularly for three-dimensional NoC (3D NoC). In this paper, authors have also presented a thermal-aware scheduling technique to test cores in 2D as well as 3D stacked NoC, using a Particle Swarm Optimization (PSO) based approach. To reduce testtime further, several innovative augmentations, such as Inversion Mutation, efficient random number generation and multiple PSO operations, have been incorporated in the basic PSO. Experimental results highlight the effectiveness of the proposed method in reducing testtime under power constraints and achieve a tradeoff between testtime and peak temperature.

PANE : Pluggable Asynchronous Network-on-Chip Simulator

Communication between different IP cores in MPSoCs and HMPs often results in clock domain crossing. Asynchronous network on chip (NoC) can supports communication in such heterogeneous set-ups. While there are a large number of tools to model NoCs for synchronous systems, there is very limited tool support to model communication for multi-clock domain NoCs and analyze them. In this paper, we propose \textbf{PANE} :Pluggable Asynchronous NEtwork on Chip simulator, that allows system level simulation of asynchronous network on chip (NoC). PANE allows exploration of synchronous, asynchronous and mixed synchronous-asynchronous(heterogeneous) design space for system level NoC parameters such as packet latencies, throughput, network saturation point. It also supports a large range of NoC configurations for both synthetic and real traffic patterns. In this paper, we also demonstrate the application of PANE by using synchronous routers, asynchronous routers and a mix of asynchronous and synchronous routers. One of the key advantages of PANE is that it allows a seamless transition from synchronous to asynchronous NoC simulators while keeping pace with the developments in synchronous NoC tools as they can be integrated with PANE.

Reliability Hardening Mechanisms in Cyber-Physical Digital-Microfluidic Biochips

In the area of biomedical engineering, digital-microfluidic biochips (DMFBs) have received considerable attention because of their capability of providing an efficient and reliable platform for conducting point-of-care clinical diagnostics. System reliability, in turn, mandates error-recoverability while implementing biochemical assays on-chip for medical applications. Unfortunately, the technology of DMFBs is not yet fully equipped to handle error-recovery from various microfluidic operations involving droplet motion and reaction. Recently, a number of cyber-physical systems have been proposed to provide real-time checking and error-recovery in assays based on the feedback received from a few on-chip checkpoints. However, in order to synthesize robust feedback systems for different types of DMFBs, certain practical issues need to be considered such as co-optimization of checkpoint placement, error-recoverability, and layout of droplet-routing pathways. For application-specific DMFBs, we propose here an algorithm that minimizes the number of checkpoints and determines their locations to cover every path in a given droplet-routing solution. Next, for general-purpose DMFBs, where the checkpoints are pre-deployed in specific locations, we present a checkpoint-aware routing algorithm such that every droplet-routing path passes through at least one checkpoint to enable error-recovery and to ensure physical routability of all droplets.

Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs

We study the ultimate limits of hardware solutions for the self-protection strategies against permanent faults in networks on chips (NoCs). NoCs reliability is improved by replacing each base router by an augmented router which includes extra protection circuitry. We compare the protection achieved by the self-test and self-protect (STAP) architectures to that of triple modular redundancy with voting (TMR). In practice, none of the considered architectures (STAP or TMR) can tolerate all the permanent faults, especially faults in the extra-circuitry for protection or voting, and consequently, there will always be some unidentified defective augmented routers which are going to transmit errors in an unpredictable manner. Specifically, we study and determine the average percentage of unidentified defective routers (UDRs) and their impact on the overall reliability of the NoC in light of self-protection strategies. Our study shows that TMR is the most efficient solution to limit the average percentage of UDRs when there are typically less than a 0.1 percent of defective base routers. Above 1% of defective base routers, the STAP approaches are more efficient although the protection efficiency decreases inexorably in the very defective technologies (e.g. when there is 10% or more of defective base routers).

System Level Analysis of 3D ICs with Thermal TSVs

3D stacking of integrated circuits (ICs) provides significant advantages in saving device footprints, improving power management, and continuing performance enhancement, particularly for many-core systems. However, the stacked structure makes the heat dissipation a challenging issue. While Thermal Through Silicon Via (TTSV) is a promising way of lowering the thermal resistance of dies, past research has either overestimated or underestimated the effects of TTSVs due to the lack of detailed 3D IC models and system-level simulations. To accurately simulate TTSV effects on 3D ICs, we adopt benchmarks from Splash-2 running on full system mode of the gem5 simulator. Gem5 generates all the system component activities and McPAT generates corresponding power consumption. Power trace of each benchmark later is fed to HotSpot for thermal simulation. The temperature of 2D and 3D Nehalem like x86 processor is compared. TTSVs are then placed close to hot spot regions of 3D ICs to facilitate vertical heat transfer to heat sink structures, the peak temperature of 3D Nehalem is reduced by 25-5% with a small area overhead of 6%. By using a detailed 3D thermal model, full system simulation, and a validated thermal simulator, our results show accurate effects of TTSVs in 3D ICs.


Publication Years 2005-2018
Publication Count 389
Citation Count 1040
Available for Download 389
Downloads (6 weeks) 1480
Downloads (12 Months) 16469
Downloads (cumulative) 162740
Average downloads per article 418
Average citations per article 3
First Name Last Name Award
Iris Bahar ACM Distinguished Member (2012)
Krishnendu Chakrabarty ACM Fellows (2013)
ACM Distinguished Member (2008)
ACM Senior Member (2006)
Jason Cong ACM Fellows (2008)
Giovanni DeMicheli ACM Fellows (2001)
Nikil D. Dutt ACM Fellows (2014)
ACM Distinguished Member (2007)
John P Hayes ACM Fellows (2001)
Niraj Jha ACM Fellows (2003)
Andrew Kahng ACM Fellows (2012)
Gabriel H Loh ACM Fellows (2017)
ACM Distinguished Member (2014)
ACM Senior Member (2009)
Roman Lysecky ACM Senior Member (2014)
Sharad Malik ACM Fellows (2014)
Igor Markov ACM Distinguished Member (2011)
ACM Senior Member (2007)
Margaret Martonosi ACM Fellows (2009)
Subhasish Mitra ACM Fellows (2014)
Dharmendra Modha ACM Gordon Bell Prize
Special Category (2009) ACM Gordon Bell Prize
Special Category (2009)
Saraju P. Mohanty ACM Senior Member (2010)
Trevor Mudge ACM Fellows (2016)
ACM-IEEE CS Eckert-Mauchly Award (2014)
Massoud Pedram ACM Distinguished Member (2008)
Dhiraj Pradhan ACM Fellows (1999)
Steven K Reinhardt ACM Distinguished Member (2010)
Rob A Rutenbar ACM Fellows (2008)
Sachin S. Sapatnekar ACM Fellows (2016)
John E Savage ACM Fellows (1996)

First Name Last Name Paper Counts
Niraj Jha 21
Krishnendu Chakrabarty 11
Kaushik Roy 9
Wei Zhang 7
Michael Niemier 6
Rodney Van Meter 6
Yuan Xie 6
Fabrizio Lombardi 6
Li Shang 6
Xiaobosharon Hu 5
Pierre Gaillardon 5
Partha Pande 5
Mehdi Tahoori 5
Morteza Zamani 4
Jiang Xu 4
Mariagrazia Graziano 4
Shuo Wang 4
Bhargab Bhattacharya 4
Mehdi Sedighi 4
Alvin Lebeck 4
Lei Wang 4
Chris Dwyer 4
Mohammad Tehranipoor 4
Paul Wettin 3
Rolf Drechsler 3
Spyros Tragoudas 3
Mahboobeh Houshmand 3
Amlan Chakrabarti 3
Jordi Cortadella 3
Vijaykrishnan Narayanan 3
Sourindra Chaudhuri 3
John Hayes 3
Yaoyao Ye 3
Anand Raghunathan 3
Tao Xu 3
Jianwei Dai 3
Aoxiang Tang 3
Xuan Wang 3
Ferdinand Peper 3
Weisheng Zhao 3
Jacques Klein 3
Fei Su 3
Arun Ravindran 3
Maurizio Zamboni 3
Nagarajan Ranganathan 3
Keshab Parhi 3
Garrett Rose 3
Eren Kursun 3
Robert Wille 3
Arindam Mukherjee 3
Tinoosh Mohsenin 3
Xiaowen Wu 3
Kishor Trivedi 3
Lei Wang 3
Michael Crocker 3
Swaroop Ghosh 3
Mahdi Nikdast 3
Xueqing Li 2
Daniel Grissom 2
Debasis Mitra 2
Vijay Reddy 2
Sumeet Gupta 2
Rangharajan Venkatesan 2
Kartik Mohanram 2
Behrooz Shirazi 2
Swarup Bhunia 2
Djaafar Chabi 2
Himanshu Thapliyal 2
Mehdi Saeedi 2
Sachin Sapatnekar 2
Giovanni De Micheli 2
Siddhartha Datta 2
Frederic Chong 2
Mrigank Sharad 2
Reza Rad 2
Mostafizur Rahman 2
Csaba Moritz 2
Zichuan Liu 2
Yu Cao 2
Chiachun Lin 2
Harika Manem 2
Jungsang Kim 2
Stefano Frache 2
Yaojun Zhang 2
Giorgio Natale 2
Lionel Torres 2
Santosh Khasanvis 2
Kolin Paul 2
Sudip Roy 2
Chris Myers 2
Douglas Densmore 2
Philip Brisk 2
Paolo Grani 2
Saibal Mukhopadhyay 2
Rivalino Matias 2
Damien Querlioz 2
Xuanyao Fong 2
Oliver Keszocze 2
Massoud Pedram 2
Bao Liu 2
Cheng Zhuo 2
Bryant Wysocki 2
John Savage 2
Giovanni Micheli 2
Jacob Murray 2
Sparsh Mittal 2
Byungsoo Choi 2
Mehrdad Nourani 2
Min Chen 2
Sungkyu Lim 2
Jing Huang 2
Alexis De Vos 2
Suman Datta 2
Ashok Palaniswamy 2
Zhehui Wang 2
André DeHon 2
Tsungyi Ho 2
Veezhinathan Kamakoti 2
Muhammad Ahsan 2
Ruth Bahar 2
Junlin Chen 2
Bharat Joshi 2
Faquir Jain 2
Philippe Coussy 2
Shashikanth Bobba 2
Pallav Gupta 2
Marco Ottavi 2
Anil Wipat 2
Josep Carmona 2
Jaidev Patwardhan 2
Avinash Kodi 2
Bipul Paul 2
Arighna Deb 2
Prateek Mishra 2
Xianmin Chen 2
Sébastien Beux 2
Baris Taskin 2
Yongtae Kim 2
Mona Arabzadeh 2
Giovanni De Micheli 2
Luca Schiano 2
Ulf Schlichtmann 2
Olivier Sentieys 2
Torben Mogensen 2
Peng Li 2
Hafizur Rahaman 2
Deliang Fan 2
Eric Rachlin 2
Dhiraj Pradhan 2
Sandro Bartolini 2
Amlan Ganguly 2
Hang Zhang 1
Keran Zhou 1
Gilles Sassatelli 1
Hui Li 1
Martha Sepúlveda 1
Smruti Sarangi 1
Mrityunjay Ghosh 1
Yu Cao 1
Dhireesha Kudithipudi 1
Pareesa Golnari 1
Mingjie Lin 1
Armin Alaghi 1
Songping Yu 1
Fang Liu 1
Yu Hu 1
Xiaowei Li 1
Marc Galceran-Oms 1
John Bainbridge 1
Aaron Dingler 1
Justin Wenck 1
Rajeevan Amirtharajah 1
Angsuman Sarkar 1
Mike Hayes 1
Weiguo Tang 1
Okan Palaz 1
Matthias Beste 1
Minhao Zhu 1
Suman Sah 1
Benjamin Belzer 1
Erik Lindgren 1
Jennifer Hallinan 1
Harold Fellermann 1
Zhiqiang Li 1
Bibhash Sen 1
H Wong 1
Franjo Ivančić 1
Martin Roetteler 1
Darshan Thaker 1
Anuroop Vidapalapati 1
Guangyu Sun 1
Masoud Zamani 1
Shunming Syu 1
S Srinivasan 1
Mohsen Raji 1
Hossein Pedram 1
Vivek Shende 1
Kwangting Cheng 1
Stephane Gros 1
Pierre Paoli 1
Chengwen Wu 1
Keqin Li 1
Wei Chen 1
Liang Wen 1
Xiong Pan 1
Luan Duong 1
Zhifei Wang 1
Luigi Carro 1
Antônio Beck 1
Ney Calazans 1
M Najafi 1
Honglan Jiang 1
Anuj Arora 1
Suyog Gupta 1
Robert Karam 1
Kyuyeon Hwang 1
Colin Shea 1
Arvind Kumar 1
Yavuz Yetim 1
Anusha Gorantla 1
Wei Chan 1
Andrew Kahng 1
Koushik Guha 1
Debasri Saha 1
Ying Wang 1
Yue Wu 1
David Clark 1
Jim Garside 1
Eustace Painkras 1
Marc Jaekel 1
Evan Lent 1
Jamie Collier 1
Clemens Moser 1
Luis Plana 1
Kele Shen 1
Rajeswari Devadoss 1
Andres Kwasinski 1
Shengqi Yang 1
Jamil Wakil 1
Robert Hannon 1
Jun Zeng 1
Mariam Momenzadeh 1
Chris Winstead 1
Ernst Oberortner 1
Tara Deans 1
Shi Xu 1
Fengbo Ren 1
Robert Patton 1
Rob Rutenbar 1
Zhengbin Pang 1
Kengo Nozaki 1
Jiating Luo 1
Daniel Chillet 1
Yi Xu 1
Stephan Menzel 1
André Stauffer 1
Pierre Mudry 1
Gianluca Tempesti 1
Andy Chiu 1
Tiansheng Zhang 1
Yue Zhang 1
Claude Chappert 1
Sungjun Yoon 1
Steven Garverick 1
Yaojoe Yang 1
Stéphane Burignat 1
Tetsuo Yokoyama 1
Alireza Shafaei 1
Misagh Khayambashi 1
Tao Li 1
Jack Sampson 1
Abbas Dehghani 1
Kamal Jamshidi 1
Jianyu Chen 1
Sylvain Claireux 1
Guangyan Zhang 1
Xuhao Chen 1
Ajay Joshi 1
Xia Zhang 1
Hassan Mohammadi 1
Matteo Reorda 1
Peng Li 1
Yong Shim 1
Eldhose Peter 1
Taemin Kim 1
Sajid Anwar 1
Nong Xiao 1
Kerry Bernstein 1
Rajit Manohar 1
Fabien Clermidy 1
Jaeyoon Kim 1
Fuwei Chen 1
Siddharth Gaba 1
Seongmin Kim 1
Yaowen Chang 1
Saeed Safari 1
Yang Zhao 1
Piero Fariselli 1
Jinho Lee 1
Kyungsu Kang 1
Naser MohammadZadeh 1
Weikai Shih 1
Nathan McDonald 1
Kethia Yao 1
Ganesh Dasika 1
Renfa Li 1
Zhe Zhang 1
Koji Inoue 1
Cédric Killian 1
Jun Yang 1
Ali Alsuwaiyan 1
Jie Chen 1
Jie Meng 1
Giacomo Indiveri 1
Can Sitik 1
Emre Salman 1
Suzanne Lesecq 1
Robert Glück 1
Indranil Sengupta 1
Jeffrey Krichmar 1
Yong Zhang 1
Benoît Miramond 1
Hugues Wouafo 1
Syed Jafri 1
Lungyen Chen 1
Laurent Becker 1
Ke Jiang 1
Peng Yang 1
Haibo Wang 1
Stephan Wong 1
Brandon Jennings 1
Steven Levitan 1
Ramy Tadros 1
Joydeep Rakshit 1
Kia Bazargan 1
Leibo Liu 1
Janibul Bashir 1
Guoqing Chen 1
Bryan Jackson 1
Kenneth O'Neal 1
Simeranjit Brar 1
Victor Nicola 1
Charles Augustine 1
Hai Li 1
Nobuaki Miyakawa 1
Chris Kim 1
Bruno Rouzeyre 1
Domenic Forte 1
Sina Shahbazmohamadi 1
Marco Indaco 1
Kae Nemoto 1
Wei Zhao 1
Nabanita Majumdar 1
Nadine Gergel-Hackett 1
Yuxing Yao 1
Gabriel Schulhof 1
Giacomo Ghidini 1
Andrew Rawson 1
Tahir Cader 1
William Gustafson 1
Aleksandr Biberman 1
Krishna Kant 1
Qianfan Xu 1
Alan Mickelson 1
Hrishikesh Jayakumar 1
Woosuk Lee 1
Aldo Romani 1
Nahid Hossain 1
Chinghwa Cheng 1
Masaki Okajima 1
Pinghung Yuh 1
Haera Chung 1
Christopher Curtis 1
Yuchun Ma 1
Tanay Karnik 1
Milad Maleki 1
Houle Gan 1
Aayush Ankit 1
Steven Young 1
Glenn Ko 1
Zhang Luo 1
Mingche Lai 1
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ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Frontiers of Hardware and Algorithms for On-chip Learning, Special Issue on Silicon Photonics and Regular Papers

Volume 14 Issue 2, July 2018 Special Issue on Frontiers of Hardware and Algorithms for On-chip Learning, Special Issue on Silicon Photonics and Regular Papers
Volume 14 Issue 1, March 2018

Volume 13 Issue 4, August 2017
Volume 13 Issue 3, May 2017 Special Issue on Hardware and Algorithms for Learning On-a-chip and Special Issue on Alternative Computing Systems
Volume 13 Issue 2, March 2017 Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era and Regular Papers

Volume 13 Issue 1, December 2016 Special Issue on Secure and Trustworthy Computing
Volume 12 Issue 4, July 2016 Regular Papers

Volume 12 Issue 3, September 2015 Special Issue on Cross-Layer System Design and Regular Papers
Volume 12 Issue 2, August 2015 Special Issue on Advances in Design of Ultra-Low Power Circuits and Systems in Emerging Technologies
Volume 12 Issue 1, July 2015
Volume 11 Issue 4, April 2015 Special Issues on Neuromorphic Computing and Emerging Many-Core Systems for Exascale Computing

Volume 11 Issue 3, December 2014 Special Issue on Computational Synthetic Biology and Regular Papers
Volume 11 Issue 2, November 2014 Special Issue on Reversible Computation and Regular Papers
Volume 11 Issue 1, September 2014
Volume 10 Issue 4, May 2014
Volume 10 Issue 3, April 2014
Volume 10 Issue 2, February 2014
Volume 10 Issue 1, January 2014 Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011

Volume 9 Issue 4, November 2013 Special Issue on Bioinformatics
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