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New JETC Editor-In-Chief

We are happy to announce that Professor Ramesh Karri will assume the role of the Editor in Chief as of August 1st. Prof. Ramesh Karri is a Professor of Electrical and Computer Engineering at Polytechnic Institute of New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research interests include trustworthy ICs and processors; High assurance nanoscale IC architectures and systems; VLSI Design and Test; Interaction between security and reliability.

He has over 150 journal and conference publications in these areas. He has written two invited articles in IEEE Computer on Trustworthy Hardware, an invited article on Digital Logic Design using Memristors in Proceedings of IEEE and an Invited article in IEEE Computer on Reliable Nanoscale Systems. These will be the basis of the Lectures that he plans to offer. He was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He served on the 2006 DARPA ISAT study on 'Trust in Integrated Circuits'. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Hardware security lead of the Center for research in interdisciplinary studies in security and privacy -CRISSP (http://crissp.poly.edu/), co-founder of the Trust-Hub (http://trust-hub.org/) and organizes the annual red team blue team event at NYU, the Embedded Systems Challenge (http://www.poly.edu/csaw2012/csaw-embedded). He cofounded and served as the chair of the IEEE Computer Society Technical Committee on Nanoscale architectures. He is a cofounder and steering committee member of the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He is the Program Chair (2012) and General Chair (2013) of IEEE Symposium on Hardware Oriented Security and Trust (HOST). He is the Program Co-Chair (2012) and General Co-Chair (2013) of IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems. He is the General Chair of the 2013 NANOARCH. He serves on several program committees. He is the Associate Editor of IEEE Transactions on Information Forensics and Security and Associate Editor of ACM Journal on Emerging Computing Technologies.

He has organized invited tutorials on various aspects of Trustworthy Hardware (including at 2012 VLSI Test Symposium, 2012 International Conference on Computer Design, 2013 IEEE North Atlantic Test Workshop, 2013 Design Automation and Test in Europe). He currently advises eight PhD students and mentors two postdoctoral candidates. His research is funded by NSF (IGERT, Scholarship for Service, Capacity Building, CRI, Cybersecurity), DOE (GAANN), AFRL, ARO, Cisco and Intel. He organizes the annual Embedded Systems Challenge to promote a challenges-based approach to hardware trust validation and embedded systems education.

 
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