enter search term and/or author name
Introduction to special section: Best of NANOARCH 2008
R. Iris Bahar
Article No.: 6
Low-power FinFET circuit synthesis using multiple supply and threshold voltages
Prateek Mishra, Anish Muttreja, Niraj K. Jha
Article No.: 7
According to Moore's law, the number of transistors in a chip doubles every 18 months. The increased transistor-count leads to increased power density. Thus, in modern circuits, power efficiency is a central determinant of circuit efficiency. With...
Defect tolerance will be critical in any system with nanoscale feature sizes. This article examines some fundamental aspects of defect tolerance for a reconfigurable system based on Quantum-dot Cellular Automata (QCA). We analyze a novel,...
Scan-chain design and optimization for three-dimensional integrated circuits
Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie
Article No.: 9
Scan chains are widely used to improve the testability of integrated circuit (IC) designs and to facilitate fault diagnosis. For traditional 2D IC design, a number of design techniques have been proposed in the literature for scan-chain routing...
Efficient parallel testing and diagnosis of digital microfluidic biochips
Siddhartha Datta, Bharat Joshi, Arun Ravindran, Arindam Mukherjee
Article No.: 10
Microfluidics-based biochips consist of microfluidic arrays on rigid substrates through which movement of fluids is tightly controlled to facilitate biological reactions. Biochips are soon expected to revolutionize biosensing, clinical...
Low-overhead defect tolerance in crossbar nanoarchitectures
Mehdi B. Tahoori
Article No.: 11
It is anticipated that the number of defects in nanoscale devices fabricated using bottom-up self-assembly process is significantly higher than that for CMOS devices fabricated by conventional top-down lithography patterning. This is mainly...