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FinFET-based power simulator for interconnection networks
Chun-Yi Lee, Niraj K. Jha
Article No.: 2
Double-gate FETs, specifically FinFETs, are emerging as promising substitutes for bulk CMOS at the 32nm technology node and beyond because of the various obstacles to scaling faced by CMOS, such as short-channel effects, leakage power, and process...
Routing in self-organizing nano-scale irregular networks
Yang Liu, Chris Dwyer, Alvin R. Lebeck
Article No.: 3
The integration of novel nanotechnologies onto silicon platforms is likely to increase fabrication defects compared with traditional CMOS technologies. Furthermore, the number of nodes connected with these networks makes acquiring a global defect...