Emerging Technologies in Computing (JETC)


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ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 8 Issue 3, August 2012

Special section on new circuit and architecture-level solutions for multidiscipline systems
Saraju P. Mohanty
Article No.: 14
DOI: 10.1145/2287696.2287697

CMOS LC voltage controlled oscillator design using multiwalled and single-walled carbon nanotube wire inductors
Ashok Srivastava, Yao Xu, Yang Liu, Ashwani K. Sharma, Clay Mayberry
Article No.: 15
DOI: 10.1145/2287696.2287698

We have utilized our Multiwalled Carbon NanoTube (MWCNT) and Single-Walled Carbon NanoTube (SWCNT) bundle interconnects model in a widely used π model to study the performances of MWCNT and SWCNT bundle wire inductors and compared these with...

Dynamic clock stretching for variation compensation in VLSI circuit design
Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman, Jr.
Article No.: 16
DOI: 10.1145/2287696.2287699

In the nanometer era, process, voltage, and temperature variations are dominating circuit performance, power, and yield. Over the past few years, statistical optimization methods have been effective in improving yield in the presence of...

Congestion-aware layout design for high-throughput digital microfluidic biochips
Sudip Roy, Debasis Mitra, Bhargab B. Bhattacharya, Krishnendu Chakrabarty
Article No.: 17
DOI: 10.1145/2287696.2287700

Potential applications of digital microfluidic (DMF) biochips now include several areas of real-life applications like environmental monitoring, water and air pollutant detection, and food processing to name a few. In order to achieve sufficiently...

Retail beamed power using millimeter waves: Survey
Narayanan Komerath, Aravinda Kar
Article No.: 18
DOI: 10.1145/2287696.2287701

Retail delivery of electric power through millimeter waves is relevant in developing areas where the market for communication devices outpaces the power grid infrastructure. It is also a critical component of an evolutionary path towards...

An efficient heuristic to identify threshold logic functions
Ashok Kumar Palaniswamy, Spyros Tragoudas
Article No.: 19
DOI: 10.1145/2287696.2287702

A fast method to identify the given Boolean function as a threshold function with weight assignment is introduced. It characterizes the function based on the parameters that have been defined in the literature. The proposed method is capable to...

Effect of process variations in 3D global clock distribution networks
Hu Xu, Vasilis F. Pavlidis, Giovanni De Micheli
Article No.: 20
DOI: 10.1145/2287696.2287703

In three-dimensional (3D) integrated circuits, the effect of process variations on clock skew differs from 2D circuits. The combined effect of inter-die and intra-die process variations on the design of 3D clock distribution networks is considered...

Spatial and temporal thermal characterization of stacked multicore architectures
Eren Kursun, Jamil Wakil, Mukta Farooq, Robert Hannon
Article No.: 21
DOI: 10.1145/2287696.2287704

Three-dimensional integration provides a new way of performance growth for microprocessor architectures. While a recent studies report promising performance improvement numbers, majority of the processor stacking options are thermally-limited....

Resilient and adaptive performance logic
Bao Liu, Xuemei Chen, Fiona Teshome
Article No.: 22
DOI: 10.1145/2287696.2287705

As VLSI technology continues scaling, increasingly significant parametric variations and increasingly prevalent defects present unprecedented challenges to VLSI design at nanometer scale. Specifically, performance variability has hindered...

Performance evaluation and design trade-offs for wireless network-on-chip architectures
Kevin Chang, Sujay Deb, Amlan Ganguly, Xinmin Yu, Suman Prasad Sah, Partha Pratim Pande, Benjamin Belzer, Deukhyoun Heo
Article No.: 23
DOI: 10.1145/2287696.2287706

Massive levels of integration are making modern multicore chips all pervasive in several domains. High performance, robustness, and energy-efficiency are crucial for the widespread adoption of such platforms. Networks-on-Chip (NoCs) have emerged...

A Θ( √ n)-depth quantum adder on the 2D NTC quantum computer architecture
Byung-Soo Choi, Rodney Van Meter
Article No.: 24
DOI: 10.1145/2287696.2287707

In this work, we propose an adder for the 2-Dimensional Nearest-Neighbor, Two-Qubit gate, Concurrent (2D NTC) architecture, designed to match the architectural constraints of many quantum computing technologies. The chosen architecture allows the...

A physical design tool for carbon nanotube field-effect transistor circuits
Jiale Huang, Minhao Zhu, Shengqi Yang, Pallav Gupta, Wei Zhang, Steven M. Rubin, Gilda Garretón, Jin He
Article No.: 25
DOI: 10.1145/2287696.2287708

In this article, we present a graphical Computer-Aided Design (CAD) environment for the design, analysis, and layout of Carbon NanoTube (CNT) Field-Effect Transistor (CNFET) circuits. This work is motivated by the fact that such a tool currently...