Emerging Technologies in Computing (JETC)


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ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era and Regular Papers, Volume 13 Issue 2, March 2017

Section: Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era

Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era
Aida Todri-Sanial, Saraju P. Mohanty, Mariane Comte, Marc Belleville
Article No.: 12
DOI: 10.1145/3003370

Exploiting Idle Hardware to Provide Low Overhead Fault Tolerance for VLIW Processors
Anderson L. Sartor, Arthur F. Lorenzon, Luigi Carro, Fernanda Kastensmidt, Stephan Wong, Antonio C. S. Beck
Article No.: 13
DOI: 10.1145/3001935

Because of technology scaling, the soft error rate has been increasing in digital circuits, which affects system reliability. Therefore, modern processors, including VLIW architectures, must have means to mitigate such effects to guarantee...

A Simplified Phase Model for Simulation of Oscillator-Based Computing Systems
Yan Fang, Victor V. Yashin, Brandon B. Jennings, Donald M. Chiarulli, Steven P. Levitan
Article No.: 14
DOI: 10.1145/2976743

Building oscillator-based computing systems with emerging nano-device technologies has become a promising solution for unconventional computing tasks like computer vision and pattern recognition. However, simulation and analysis of these computing...

A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits
Ajay Singhvi, Matheus T. Moreira, Ramy N. Tadros, Ney L. V. Calazans, Peter A. Beerel
Article No.: 15
DOI: 10.1145/2948067

Contemporary digitally controlled delay elements (DEs) trade off power overheads and delay quantization error (DQE). This article proposes a new programmable DE that provides a balanced design that yields low power with moderate DQE even under...

A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors
Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sanchez, Matteo Sonza Reorda
Article No.: 16
DOI: 10.1145/2988234

This article first explores the effects of faults on circuits implemented with controllable-polarity transistors. We propose a new fault model that suits the characteristics of these devices, and we report the results of a SPICE-based analysis of...

Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices
Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatie
Article No.: 17
DOI: 10.1145/3001936

Over the past few years, a new era of smart connected devices has emerged in the market to enable the future world of the Internet of Things (IoT). A key requirement for IoT applications is the power consumption to allow very high autonomy in the...

Monolayer Transistor SRAMs: Toward Low-Power, Denser Memory Systems
Joydeep Rakshit, Kartik Mohanram, Runlai Wan, Kai Tak Lam, Jing Guo
Article No.: 18
DOI: 10.1145/2967613

Monolayer heterojunction FETs based on vertical heterogeneous transition metal dichalcogenides (TMDCFETs) and planar black phosphorus FETs (BPFETs) have demonstrated excellent subthreshold swing, high IONIOFF,...

Section: Regular Papers

Alleviate Chip Pin Constraint for Multicore Processor by On/Off-Chip Power Delivery System Codesign
Xuan Wang, Jiang Xu, Zhe Wang, Haoran Li, Zhehui Wang, Peng Yang, Luan H. K. Duong, Rafael K. V. Maeda, Zhifei Wang
Article No.: 19
DOI: 10.1145/2914791

The number of chip pins is limited due to the cost and reliability issues of sophisticated packages, and it is predicted that the chip pin count will be overstretched to satisfy the requirements of both power delivery and memory access. The gap...

Yield, Area, and Energy Optimization in STT-MRAMs Using Failure-Aware ECC
Zoha Pajouhi, Xuanyao Fong, Anand Raghunathan, Kaushik Roy
Article No.: 20
DOI: 10.1145/2934685

Spin-Transfer Torque MRAMs are attractive due to their non-volatility, high density, and zero leakage. However, STT-MRAMs suffer from poor reliability due to shared read and write paths. Additionally, conflicting requirements for data retention...

Optimized Standard Cells for All-Spin Logic
Meghna G. Mankalale, Sachin S. Sapatnekar
Article No.: 21
DOI: 10.1145/2967612

All-Spin Logic (ASL) devices provide a promising spintronics-based alternative for Boolean logic implementations in the post-Complementary Metal-Oxide Semiconductor (CMOS) era. In principle, any logic functionality can be implemented in ASL. In...

System-Level Design to Detect Fault Injection Attacks on Embedded Real-Time Applications
Wei Jiang, Liang Wen, Ke Jiang, Xia Zhang, Xiong Pan, Keran Zhou
Article No.: 22
DOI: 10.1145/2967611

Fault injection attack has been a serious threat to security-critical embedded systems for a long time, yet existing research ignores addressing of the problem from a system-level perspective. This article presents an approach to the synthesis of...

Asymmetric Underlapped FinFETs for Near- and Super-Threshold Logic at Sub-10nm Technology Nodes
A. Arun Goud, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
Article No.: 23
DOI: 10.1145/2967615

Extending double-gate FinFET scaling to sub-10nm technology regime requires device-engineering techniques for countering the rise of direct source to drain tunneling (DSDT), edge direct tunneling (EDT) and short channel effects (SCE) that degrade...

Electro-Photonic NoC Designs for Kilocore Systems
José L. Abellán, Chao Chen, Ajay Joshi
Article No.: 24
DOI: 10.1145/2967614

The increasing core count in manycore systems requires a corresponding large Network-on-chip (NoC) bandwidth to support the overlying applications. However, it is not possible to provide this large bandwidth in an energy-efficient manner using...

One-Step Sneak-Path Free Read Scheme for Resistive Crossbar Memory
Yao Wang, Liang Rong, Haibo Wang, Guangjun Wen
Article No.: 25
DOI: 10.1145/3012002

A one-step sneak-path free read scheme for resistive crossbar memory is proposed in this article. During read operation, it configures the crossbar array into a four-terminal resistance network, which is composed of the selected cell and three...

Ultra-low-leakage, Robust FinFET SRAM Design Using Multiparameter Asymmetric FinFETs
Abdullah Guler, Niraj K. Jha
Article No.: 26
DOI: 10.1145/2988233

Memory arrays consisting of Static Random Access Memory (SRAM) cells occupy the largest area on chip and are responsible for significant leakage power consumption in modern microprocessors. With the transition from planar Complementary...

Shielding STT-RAM Based Register Files on GPUs against Read Disturbance
Hang Zhang, Xuhao Chen, Nong Xiao, Lei Wang, Fang Liu, Wei Chen, Zhiguang Chen
Article No.: 27
DOI: 10.1145/2996191

To address the high energy consumption issue of SRAM on GPUs, emerging Spin-Transfer Torque (STT-RAM) memory technology has been intensively studied to build GPU register files for better energy-efficiency, thanks to its benefits of low leakage...

Source Authentication Techniques for Network-on-Chip Router Configuration Packets
Arnab Kumar Biswas
Article No.: 28
DOI: 10.1145/2996194

It is known that maliciously configured Network-on-Chip routers can enable an attacker to launch different attacks inside a Multiprocessor System-on-Chip. A source authentication mechanism for router configuration packets can prevent such...

A Survey of Techniques for Architecting Processor Components Using Domain-Wall Memory
Sparsh Mittal
Article No.: 29
DOI: 10.1145/2994550

Recent trends of increasing core-count and bandwidth/memory wall have motivated researchers to explore novel memory technologies for designing processor components such as cache, register file, shared memory, and so on. Domain-wall memory (DWM),...