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An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators
Neel Gala, Sarada Krithivasan, Wei-Yu Tsai, Xueqing Li, Vijaykrishnan Narayanan, V. Kamakoti
Article No.: 1
As we enter an era witnessing the closer end of Dennard scaling, where further reduction in power supply-voltage to reduce power consumption becomes more challenging in conventional systems, a goal of developing a system capable of performing...
Design Considerations for Memristive Crossbar Physical Unclonable Functions
Mesbah Uddin, MD. Badruddoja Majumder, Karsten Beckmann, Harika Manem, Zahiruddin Alamgir, Nathaniel C. Cady, Garrett S. Rose
Article No.: 2
Hardware security has emerged as a field concerned with issues such as integrated circuit (IC) counterfeiting, cloning, piracy, and reverse engineering. Physical unclonable functions (PUF) are hardware security primitives useful for mitigating...
Statistical Optimization of FinFET Processor Architectures under PVT Variations Using Dual Device-Type Assignment
Ye Yu, Niraj K. Jha
Article No.: 3
With semiconductor technology scaling to the 22nm node and beyond, fin field-effect transistor (FinFET) has started replacing complementary metal-oxide semiconductor (CMOS), thanks to its superior control of short-channel effects and much lower...
Heterogeneous HMC+DDRx Memory Management for Performance-Temperature Tradeoffs
Mohammad Hossein Hajkazemi, Mohammad Khavari Tavana, Tinoosh Mohsenin, Houman Homayoun
Article No.: 4
Three-dimensional DRAMs (3D-DRAMs) are emerging as a promising solution to address the memory wall problem in computer systems. However, high fabrication cost per bit and thermal issues are the main reasons that prevent architects from using...
Robust In-Field Testing of Digital Microfluidic Biochips
Sukanta Bhattacharjee, Debasis Mitra, Bhargab B. Bhattacharya
Article No.: 5
Microfluidic technology offers vast promise for implementing biochemistry-on-chip with diverse applications to clinical diagnosis, genome analysis, drug design, and point-of-care testing. Among various types of fluid-chips, droplet-based digital...
Improving AES Core Performance via an Advanced ASBUS Protocol
Xiaokun Yang, Wujie Wen, Ming Fan
Article No.: 6
Security is becoming a de-facto requirement of System-on-Chips (SoC), leading up to a significant share of circuit design cost. In this article, we propose an advanced SBUS protocol (ASBUS), to improve the data feeding efficiency of the Advanced...
Resource-Constrained Scheduling for Digital Microfluidic Biochips
Kenneth O'neal, Daniel Grissom, Philip Brisk
Article No.: 7
Digital microfluidics based on electrowetting-on-dielectric technology is poised to revolutionize many aspects of chemistry and biochemistry through miniaturization, automation, and software programmability. Digital microfluidic biochips (DMFBs)...
Impact of Process Variation on Self-Reference Sensing Scheme and Adaptive Current Modulation for Robust STTRAM Sensing
Seyedhamidreza Motaman, Swaroop Ghosh, Jaydeep Kulkarni
Article No.: 8
Spin-Transfer-Torque RAM (STTRAM) is a promising technology for high-density on-chip cache due to low standby power and high speed. However, the process variation of the Magnetic Tunnel Junction (MTJ) and access transistor poses a serious...
Wireless Network-on-Chip (WiNoC) represents a promising emerging communication technology for addressing the scalability limitations of future manycore architectures. In a WiNoC, high-latency and power-hungry long-range multi-hop communications...
Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM
Bohua Li, Yukui Pei, Wujie Wen
Article No.: 10
Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings, have...
Online Adaptation and Energy Minimization for Hardware Recurrent Spiking Neural Networks
Yu Liu, Yingyezhe Jin, Peng Li
Article No.: 11
The Liquid State Machine (LSM) is a promising model of recurrent spiking neural networks that provides an appealing brain-inspired computing paradigm for machine-learning applications such as pattern recognition. Moreover, processing information...
Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs
Paolo Grani, Sandro Bartolini
Article No.: 12
Nanophotonics is a promising solution for on-chip interconnection due to its intrinsic low-latency and low-power features, which can be useful for performance and energy in future Chip Multi-Processors (CMPs).
This article proposes a novel...
A Quantum Computing Performance Simulator Based on Circuit Failure Probability and Fault Path Counting
Andre Van Rynbach, Muhammad Ahsan, Jungsang Kim
Article No.: 13
Quantum computing performance simulators are needed to provide practical metrics for the effectiveness of executing theoretical quantum information processing protocols on physical hardware. In this work, we present a tool to simulate the...