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Guest Editors’ Introduction: Frontiers of Hardware and Algorithms for On-chip Learning
Yu Cao, Xin Li, Jae-Sun Seo, Ganesh Dasika
Article No.: 14
Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics
Hyungjun Kim, Taesu Kim, Jinseok Kim, Jae-Joon Kim
Article No.: 15
Artificial Neural Network computation relies on intensive vector-matrix multiplications. Recently, the emerging nonvolatile memory (NVM) crossbar array showed a feasibility of implementing such operations with high energy efficiency. Thus, there...
Energy-Efficient Neural Computing with Approximate Multipliers
Syed Shakib Sarwar, Swagath Venkataramani, Aayush Ankit, Anand Raghunathan, Kaushik Roy
Article No.: 16
Neural networks, with their remarkable ability to derive meaning from a large volume of complicated or imprecise data, can be used to extract patterns and detect trends that are too complex for the von Neumann computing paradigm. Their...
Real-Time and Low-Power Streaming Source Separation Using Markov Random Field
Glenn G. Ko, Rob A. Rutenbar
Article No.: 17
Machine learning (ML) has revolutionized a wide range of recognition tasks, ranging from text analysis to speech to vision, most notably in cloud deployments. However, mobile deployment of these ideas involves a very different category of design...
A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks
Yixing Li, Zichuan Liu, Kai Xu, Hao Yu, Fengbo Ren
Article No.: 18
FPGA-based hardware accelerators for convolutional neural networks (CNNs) have received attention due to their higher energy efficiency than GPUs. However, it is challenging for FPGA-based solutions to achieve a higher throughput than GPU...
A Study of Complex Deep Learning Networks on High-Performance, Neuromorphic, and Quantum Computers
Thomas E. Potok, Catherine Schuman, Steven Young, Robert Patton, Federico Spedalieri, Jeremy Liu, Ke-Thia Yao, Garrett Rose, Gangotree Chakma
Article No.: 19
Current deep learning approaches have been very successful using convolutional neural networks trained on large graphical-processing-unit-based computers. Three limitations of this approach are that (1) they are based on a simple layered network...
Silicon Photonics for Computing Systems
Jiang Xu, Yuichi Nakamura, Andrew Kahng
Article No.: 20
A Learning-Based Thermal-Sensitive Power Optimization Approach for Optical NoCs
Zhe Zhang, Yaoyao Ye
Article No.: 21
Optical networks-on-chip (NoCs) based on silicon photonics have been proposed as emerging on-chip communication architectures for chip multiprocessors with large core counts. However, due to the thermal sensitivity of optical devices used in...
A Process-Variation-Tolerant Method for Nanophotonic On-Chip Network
Yi Xu, Jun Yang, Rami Melhem
Article No.: 22
Nanophotonic networks, a potential candidate for future networks on-chip, have been challenged for their reliability due to several device-level limitations. One of the main issues is that fabrication errors (a.k.a. process variations) can cause...
Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping
Edoardo Fusella, Alessandro Cilardo
Article No.: 23
To face the complex communication problems that arise as the number of on-chip components grows up, photonic networks-on-chip (NoCs) have been recently proposed to replace electronic interconnects. However, photonic NoCs lack efficient laser...
Offline Optimization of Wavelength Allocation and Laser Power in Nanophotonic Interconnects
Jiating Luo, Cedric Killian, Sebastien Le Beux, Daniel Chillet, Olivier Sentieys, Ian O’connor
Article No.: 24
Optical Network-on-Chip (ONoC) is a promising communication medium for large-scale multiprocessor systems-on-chips. Indeed, ONoC can outperform classical electrical NoCs in terms of energy efficiency and bandwidth density, in particular, because...
SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip
Scott Vanwinkle, Avinash Karanth Kodi
Article No.: 25
As the relentless quest for higher throughput and lower energy cost continues in heterogenous multicores, there is a strong demand for energy-efficient and high-performance Network-on-Chip (NoC) architectures. Heterogeneous architectures that can...
An Integrated Nanophotonic Parallel Adder
Tohru Ishihara, Akihiko Shinya, Koji Inoue, Kengo Nozaki, Masaya Notomi
Article No.: 26
Integrated optical circuits with nanophotonic devices have attracted significant attention due to their low power dissipation and light-speed operation. With light interference and resonance phenomena, the nanophotonic device works as a...
An on-chip optical transceiver for transmission system over 100GBd is proposed based on optical time division multiplexing (OTDM) technology, and the performances, such as the insertion loss, the inter-symbol interference (ISI) crosstalk, and the...
MFNW: An MLC/TLC Flip-N-Write Architecture
Ali Alsuwaiyan, Kartik Mohanram
Article No.: 28
The increased capacity of multi-level cells (MLC) and triple-level cells (TLC) in emerging non-volatile memory (NVM) technologies comes at the cost of higher cell write energies and lower cell endurance. In this article, we describe MFNW, a...
A Chip-Level Anti-Reverse Engineering Technique
Shuai Chen, Junlin Chen, Lei Wang
Article No.: 29
Protection of intellectual property (IP) is increasingly critical for IP vendors in the semiconductor industry. However, advanced reverse engineering techniques can physically disassemble the chip and derive the IPs at a much lower cost than the...
Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays
Debjyoti Bhattacharjee, Anne Siemon, Eike Linn, Stephan Menzel, Anupam Chattopadhyay
Article No.: 30
Low operating voltage, high storage density, non-volatile storage capabilities, and relative low access latencies have popularized memristive devices as storage devices. Memristors can be ideally used for in-memory computing in the form of hybrid...